Patent Assignment
Reel/Frame 037147/0487
Assignment of Assignor's Interest
Recorded: 2015-11-19
Pages: 12
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, IRELAND
Covered Properties
(186)
Current Control Circuit and Method for Programmable Read Write Preamplifier
Patent:
5,790,331 →
Application:
08/514,120 →
System and Method for Encoding Data Such That After Precoding the Data Has a Pre-Selected Parity Structure
Patent:
5,809,081 →
Application:
08/650,700 →
System and Method for Generating Many Ones Codes with Hamming Distance After Precoding
Patent:
6,084,535 →
Application:
08/791,687 →
Method for Manufacturing a Resistively Switching Memory Cell and Memory Device Based Thereon
Processing Arrangement, Memory Card Device and Method for Operating and Manufacturing a Processing Arrangement
Semiconductor Memory Device with Channel Regions Along Sidewalls of Fins
Gate Induced Drain Leakage Current Reduction by Voltage Regulation of Master Wordline
Write Burst Stop Function in Low Power Ddr Sdram
Resistive Memory Device and Method for Writing to a Resistive Memory Cell in a Resistive Memory Device
Edge Pad Architecture for Semiconductor Memory
Method of Manufacturing a Field Effect Transistor Device with Recessed Channel and Corner Gate Device
Test Mode for Ipp Current Measurement for Wordline Defect Detection
Integrated Circuit Having a Resistive Memory
Integrated Circuit Memory Having a Read Circuit
Memory Device and a Method of Forming a Memory Device
Memory Data Bus Structure and Method of Transferring Information with Plural Memory Banks
Test Parallelism Increase by Tester Controllable Switching of Chip Select Groups
System Method for Performing a Direct Memory Access for Automatically Copying Initialization Boot Code in a New Memory Architecture
Storage Capacitor for Semiconductor Memory Cells and Method of Manufacturing a Storage Capacitor
Clock and Data Recovery Circuit Having Gain Control
Data Handover Unit for Transferring Data Between Different Clock Domains by Parallelly Reading Out Data Bits from a Plurality of Storage Elements
Shared Interface for Components in an Embedded System
Method and Apparatus for Calibration of an on-Chip Temperature Sensor Within a Memory Device
Method and Apparatus for an Oscillator Within a Memory Device
Phase Change Memory Fabricated Using Self-Aligned Processing
Phase Change Memory Fabricated Using Self-Aligned Processing
Methods for Generating a Reference Voltage and for Reading a Memory Cell and Circuit Configurations Implementing the Methods
Integrated Semiconductor Memory Device
Method for Determining an Edge Profile of a Volume of a Photoresist After a Development Process
Memory Circuit, Method for Operating a Memory Circuit, Memory Device and Method for Producing a Memory Device
Integrated Circuit Having A Memory Cell
Hard Mask Layer Stack and a Method of Patterning
Intergrated Circuit Including Resistivity Changing Material Element
Parallel Read for Front End Compression Mode
Memory with a Temperature Sensor, Dynamic Memory and Memory with a Clock Unit and Method of Sensing a Temperature of a Memory
Finding a Data Pattern in a Memory
Memory Including a Write Training Block
Filtering Bit Position in a Memory
Memory Including an Output Pointer Circuit
Reducing Leakage Current in Memory Device Using Bitline Isolation
Manufacturing Method for an Integrated Semiconductor Structure
Method for Forming an Integrated Memory Device and Memory Device
Charge Trapping Device and Method of Producing the Charge Trapping Device
Methods of Ddr Receiver Read Re-Synchronization
Memory Having Storage Locations Within a Common Volume of Phase Change Material
Method for Programming a Block of Memory Cells, Non-Volatile Memory Device and Memory Card Device
Duty Cycle Corrector
Integrated Circuit Including Sidewall Spacer
Circuit and a Method of Determining the Resistive State of a Resistive Memory Cell
System and Method to Synchronize Signals in Individual Integrated Circuit Components
Data Inversion Device and Method
Integrated Circuit Having a Switch
Bitline Leakage Limiting with Improved Voltage Regulation
Vertical Device with Sidewall Spacer, Methods of Forming Sidewall Spacers and Field Effect Transistors, and Patterning Method
Method and Apparatus for Early Write Termination in a Semiconducutor Memory
Phase Change Memory Having Temperature Budget Sensor
Thermal Isolation of Phase Change Memory Cells
Method for Producing a Dielectric Interlayer and Storage Capacitor with Such a Dielectric Interlayer
Semiconductor Memory Module
Memory Cell Array and Method of Forming a Memory Cell Array
Integrated Memory Device and Method for Its Testing and Manufacture
Manufacturing Method for an Integrated Semiconductor Structure
Memory Device, in Particular Phase Change Random Access Memory Device with Transistor, and Method for Fabricating a Memory Device
Programmable Resistive Memory Cell with a Programmable Resistance Layer
Random Access Memory Including Multiple State Machines
Memory Cell Programmed Using a Temperature Controlled Set Pulse
Method for Accessing a Non-Volatile Memory via a Volatile Memory Interface
Apparatus and Method for Controlling a Driver Strength
Memory System and Method for Operating a Memory System
Integrated Circuit Package with a Heat Dissipation Device
Method and Circuit for Transmitting a Memory Clock Signal
Transistor, Memory Cell Array and Method for Forming and Operating a Memory Device
Memory Device and Method for Transforming Between Non-Power-of-2 Levels of Multilevel Memory Cells and 2-Level Data Bits
Method and Device for Verifying Output Signals of an Integrated Circuit
Sputter Deposition Method for Forming Integrated Circuit
Die Configurations and Methods of Manufacture
Method for Forming a Capacitor Structure
Buried Bitline with Reduced Resistance
Memory Device, and Method for Operating a Memory Device
Semiconductor Device with Stacked Chips and Method for Manufacturing Thereof
Integrated Circuit Having a Phase Change Memory Cell Including a Narrow Active Region Width
Method of Manufacturing at Least One Semiconductor Component and Memory Cells
Method and System for Trimming Voltage or Current References
Random Access Memory That Selectively Provides Data to Amplifiers
Integrated Circuit with Memory Having a Step-Like Programming Characteristic
Method for Manufacturing a Capacitor Electrode Structure
Phase Change Memory Cell Including Nanocomposite Insulator
Boosted Clock Circuit for Semiconductor Memory
Method of Forming a Doped Portion of a Semiconductor and Method of Forming a Transistor
Data Sampler Including a First Stage and a Second Stage
Memory System
Method for Placing Material Onto a Target Board by Means of a Transfer Board
Shielded Circuit Board and Method for Shielding a Circuit Board
Method of Forming a Semiconductor Device
Memory Element Comprising Non-Graphitic Disorered Carbon and Using Reversible Switiching Between SP2 and SP3 Hybirdization States
Filter System for Light Source
Transistor, Memory Cell Array and Method of Manufacturing a Transistor
Transistor and Memory Cell Array
Integrated Memory Cell Array
Method and Apparatus for Sending Data from a Memory
Memory Circuit, a Dynamic Random Access Memory, a System Comprising a Memory and a Floating Point Unit and a Method for Storing Digital Data
Method of Forming a Semiconductor Memory Device and Semiconductor Memory Device
Evaluation Circuit and Evaluation Method for the Assessment of Memory Cell States
Semiconductor Device Including Multi-Bit Memory Cells and a Temperature Budget Sensor
Method for Manufacturing a Structure in a Semiconductor Device and a Structure in a Semiconductor Device
Error Correction in Memory Devices
Manufacturing Method for an Integrated Semiconductor Structure
Modifiable Gate Stack Memory Element
Solder Pillar Bumping and a Method of Making the Same
System That Prevents Reduction in Data Retention
Output Driver
Die and Wafer Failure Classification System and Method
Arrangement of Semiconductor Memory Devices and Semiconductor Memory Module Comprising an Arrangement of Semiconductor Memory Devices
Measuring Method for a Semiconductor Memory, and Semiconductor Memory
Phase Change Random Access Memory Device with Transistor, and Method for Fabricating a Memory Device
Pillar Phase Change Memory Cell
High Density Memory Array for Low Power Application
Method and Device for Determining Trim Solution
Deposition Method for a Transition-Metal-Containing Dielectric
Semiconductor Component Comprising an Integrated Semiconductor Chip and a Chip Housing, and Electronic Device
Method for Producing a Mask for the Lithographic Projection of a Pattern Onto a Substrate
Integrated Circuit for Receiving Data
Method of Removing Refractory Metal Layers and of Siliciding Contact Areas
Asynchronous Data Transmission
Integrated Semiconductor Memory Devices with Generation of Voltages
3-D Channel Field-Effect Transistor, Memory Cell and Integrated Circuit
Memory Arrangement
Memory Arrangement Having Efficient Arrangement of Devices
Integrated Device for Simplified Parallel Testing, Test Board for Testing a Plurality of Integrated Devices, and Test System and Tester Unit
Integrated Circuits, Methods for Manufacturing Integrated Circuits, Integrated Memory Arrays
Methods for Forming an Integrated Circuit, Including Openings in a Mold Layer from Nanowires or Nanotubes
Semiconductor Device, Method for Manufacturing a Semiconductor Device and Mask for Manufacturing a Semiconductor Device
Carbon Filament Memory and Fabrication Method
Integrated Semiconductor Memory
Integrated Semiconductor Memory with Generation of Data
Memory Device and Method of Operating Such
Memory Device, Memory System and Method of Operating Such
Memory Circuit Having Memory Chips Parallel Connected to Ports and Corresponding Production Method
Memory-Module Controller, Memory Controller and Corresponding Memory Arrangement, and Also Method for Error Correction
Data Receiver with Clock Recovery Circuit
System and Method for Projecting a Pattern from a Mask Onto a Substrate
Electrical Through Contact
Integrated Semiconductor Memory and Method for Operating an Integrated Semiconductor Memory
Minority Carrier Sink for a Memory Cell Array Comprising Nonvolatile Semiconductor Memory Cells
Integrated Semiconductor Memory Device with Clock Generation
Memory with an Output Register for Test Data and Process for Testing a Memory and Memory Module
Integrated Electrical Module with Regular and Redundant Elements
Memory Having Shared Storage Material
Apparatus for Filtering Signals
Memory with Clock-Controlled Memory Access and Method of Operating the Same
Method for Applying Solder to Redistribution Lines
Method for Accessing a Memory
Method and Protective Circuit Against Overvoltage
Integrated Semiconductor Memory with Distributor Line for Redundant Data Lines
Memory Buffer for an Fb-Dimm
Method and Device for Classifying Cells in a Layout into a Same Environment and Their Use for Checking the Layout of an Electronic Circuit
Integrated Circuit Having a Cell with a Resistivity Changing Layer
Method and Device for Handling an Article in the Course of Semiconductor Fabrication
Device for Refreshing Memory Contents
Method of Manufacturing a Transistor and Memory Cell Array
Memory Chip Having a Complex Termination
Method for Producing a Circuit Module Comprising at Least One Integrated Circuit
Integrated Circuit for Sampling a Sequence of Data Packets at a Data Output
Refreshing the Content of a Memory Cell of a Memory Arrangement
Memory Apparatus with a Bus Architecture
Device and Method Including Current Measurement and/or Amplification
Method and Apparatus for Adjusting the Timing of an Electronic Circuit
Delay Circuit
Semiconductor Device with Different Conductive Features Embedded in a Mold Enclosing a Semiconductor Die and Method for Making Same
Integrated Circuit Including a Memory Module Having a Plurality of Memory Banks
Integrated Circuit Including Data Synchronization Apparatus and Method
Memory Module and Method for Operating a Memory Module
Test Method and Semiconductor Device
Method and Apparatus for Testing a Memory Chip Using a Common Node for Multiple Inputs and Outputs
Write Access and Subsequent Read Access to a Memory Device
Integrated Circuits, Memory Controller, and Memory Modules
Integrated Circuit Including a Memory Fabricated Using Self-Aligned Processing
Resistive Memory Element and Method of Fabrication
Memory Element with Positive Temperature Coefficient Layer
Semiconductor Memory and Method for Operating a Semiconductor Memory
Method for Producing a Dielectric Interlayer and Storage Capacitor with Such a Dielectric Interlayer
Integrated Circuit with Memory Having a Current Limiting Switch
Method and Apparatus for Performing Internal Hidden Refreshes While Latching Read/Write Commands, Address and Data Information for Later Operation
Semiconductor Memory Module, Electronic Apparatus and Method for Operating Thereof
Patent:
43,162 →
Application:
12/759,827 →
Integrated Device
Application:
13/050,645 →
Publication:
US 2011/0162204
Memory-Module Controller, Memory Controller and Corresponding Memory Arrangement, and Also Method for Error Correction
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 27, 2012
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 028853/0605 →
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest
Nov 30, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037171/0719 →