IP Library Granted Patent US 7,564,718
Granted Patent B2
US 7,564,718 · App. 11/402,649 · Granted Jul 21, 2009

Method for programming a block of memory cells, non-volatile memory device and memory card device

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Quick Facts
Patent No.
US 7,564,718
App. No.
11/402,649
Granted
Jul 21, 2009
Kind
B2
Abstract

A method is provided for programming a block of memory cells of a non-volatile memory device. A first group of memory cells of the block of memory cells is selected. At least one programming pulse is programmed into all memory cells of the first group. A threshold level is detected for each one of the memory cells of the first group only. The first group of memory cells is verified by comparing each one of the detected threshold levels with predefined target levels provided for each one of the first group of memory cells.

Claims (52)

1. A method for programming a block of memory cells of a non-volatile memory device, the method comprising;

detecting a first threshold level for each one of the memory cells of the block of memory cells;

verifying the block of memory cells by comparing each one of the first detected threshold levels with predefined target levels provided for each one of the memory cells of the block of memory cells;

selecting all memory cells that are verified unsuccessfully as a first group of memory cells;

programming at least one programming pulse into all memory cells of the first group;

detecting a threshold level for each one of the memory cells of the first group only; and

verifying the first group of memory cells by comparing each one of the detected threshold levels with predefined target levels provided for each one of the first group of memory cells.

2. The method according to claim 1 , wherein the steps of programming, detecting and verifying are performed repeatedly, until all memory cells of the first group of memory cells have been verified successfully.

3. The method according to claim 2 , wherein, in the step of verifying the first group of memory cells, memory cells that have been verified successfully are removed from the first group, such that, when the first group is empty, all memory cells of the first group of memory cells have been verified successfully.

4. The method according to claim 1 , wherein at least some of the memory cells of the first group of memory cells are verified sequentially.

5. The method according to claim 1 , wherein at least some of the memory cells of the first group of memory cells are verified in parallel.

6. A method for programming a block of memory cells of a non-volatile memory device, the method comprising:

selecting memory cells of the block of memory cells that are to be programmed to a programmed state as a first group; and

while the first group contains at least one memory cell, performing the steps of:

programming at least one programming pulse into all memory cells of the first group;

detecting a threshold level for each one of the memory cells of the first group only;

comparing each one of the detected threshold levels with a predefined target level associated with the programmed state; and

reassigning the first group such that it only contains memory cells whose threshold level is below the predefined target level associated with the programmed state.

7. The method according to claim 6 , wherein the block of memory cells is prepared for programming using the following steps:

programming all memory cells of the block of memory cells to the programmed state; and

programming all memory cells of the block of memory cells to an erased state.

8. A method for programming a block of memory cells of a non-volatile memory device, the method comprising:

selecting a first group of memory cells of the block of memory cells; and

while the first group contains at least one memory cell, performing the steps of:

programming at least one programming pulse into all memory cells of the first group;

detecting a threshold level for each one of the memory cells of the first group only; and

removing the memory cells from the first group, if a detected level of the memory cell lies within a predefined target range.

9. A memory card device, comprising:

an array of non-volatile memory cells;

a column decoder coupled to the array;

at least one write circuit coupled to the array;

at least one sense amplifier coupled to the array; and

a micro-controller, wherein the micro-controller is adapted to perform a computer program for causing the execution of the steps of:

detecting a first threshold level for each one of the memory cells of the block of memory cells;

verifying the block of memory cells by comparing each one of the first detected threshold levels with predefined target levels provided for each one of the memory cells of the block of memory cells;

selecting all memory cells that are verified unsuccessfully as a first group of memory cells;

programming at least one programming pulse into all memory cells of the first group;

detecting a threshold level for each one of the memory cells of the first group only; and

verifying the first group of memory cells by comparing each one of the detected threshold levels with predefined target levels provided for each one of the first group of memory cells.

10. The memory card device according to claim 9 wherein the steps of programming, detecting and verifying are performed repeatedly, until all memory cells of the first group of memory cells have been verified successfully.

11. A non-volatile memory device comprising:

an array of non-volatile memory cells;

a column decoder coupled to the array;

at least one write circuit coupled to the array;

at least one sense amplifier coupled to the array; and

a micro-controller, wherein the micro-controller is adapted to perform a computer program for causing the execution of the steps of:

selecting memory cells of the block of memory cells that are to be programmed to a programmed state as a first group; and

while the first group contains at least one memory cell, performing the steps of:

programming at least one programming pulse into all memory cells of the first group;

detecting a threshold level for each one of the memory cells of the first group only;

comparing each one of the detected threshold levels with a predefined target level associated with the programmed state; and

reassigning the first group such that it only contains memory cells whose threshold level is below the predefined target level associated with the programmed state.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037171/0719 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037147/0487 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2010
From: INFINEON TECHNOLOGIES FLASH GMBH & CO. KG
To: QIMONDA AG
Reel/Frame 023806/0393 →