Memory cell programmed using a temperature controlled set pulse
View Patent ↗A memory device includes a phase change memory cell and a circuit. The circuit is for programming the memory cell to a selected one of more than two states by applying a temperature controlled set pulse to the memory cell.
1. A memory device comprising:
a phase change memory cell; and
a circuit for monitoring a resistance of the memory cell for detecting the memory cell temperature and for programming the memory cell to a selected one of more than two states having resistances different from the monitored resistance by applying a temperature controlled set pulse to the memory cell, the temperature controlled set pulse based on the detected temperature of the memory cell as indicated by the monitored resistance;
wherein the temperature controlled set pulse comprises applying a current to the memory cell, ramping up the current and leveling the current in response to the monitored resistance reaching a desired value, maintaining the current level for a set period to set the memory cell to the selected state, and ramping down the current once the set period has elapsed.
2. The memory of claim 1 , wherein the temperature controlled set pulse comprises applying the current to the memory cell to reach a threshold voltage of the memory cell.
3. The memory of claim 1 , wherein the set period comprises a crystallization time of the memory cell at the desired value.
4. The memory of claim 1 , wherein the phase change memory cell comprises one of Ge, Sb, Te, Ga, As, In, Se, and S.
5. An integrated circuit comprising:
a phase change memory cell; and
a circuit for monitoring a resistance of the memory cell to detect the memory cell temperature and for programming the memory cell to a selected state of more than two possible states,
wherein the circuit programs the memory cell by applying a current to the memory cell, thereby ramping up the current and leveling the current in response to the resistance reaching a desired value, maintaining the current level for a set period to set the memory cell to the selected state, and ramping down the current once the set period has elapsed.
6. The integrated circuit of claim 5 , wherein the circuit monitors the resistance of the memory cell based on a voltage across the memory cell.
7. The integrated circuit of claim 5 , wherein the desired value is based on the selected state.
8. The integrated circuit of claim 5 , wherein the set period comprises a crystallization time of the memory cell at the desired value.
9. The integrated circuit of claim 5 , wherein the phase change memory cell comprises one of Ge, Sb, Te, Ga, As, In, Se, and S.
10. A memory comprising:
a phase change memory cell for storing at least 1.5 data bits; and
means for programming the memory cell using a temperature controlled set pulse comprising:
means for ramping up a current of the set pulse;
means for monitoring a resistance of the memory cell to detect the memory cell temperature and leveling the current in response to the resistance reaching a desired value;
means for maintaining the current level for a set period to set the memory cell to a desired state; and
means for ramping down the current once the set period has elapsed.
11. The memory of claim 10 , wherein the means for programming the memory cell using the temperature controlled set pulse further comprises:
means for reaching a threshold voltage of the memory cell.
12. The memory of claim 10 , wherein the set period comprises a crystallization time of the memory cell at the desired value.
13. The memory of claim 10 , wherein the phase change memory cell comprises one of Ge, Sb, Te, Ga, As, In, Se, and S.
14. A method for programming a phase change memory cell, the method comprising:
resetting the memory cell to an amorphous state;
applying a current to the memory cell;
ramping up the current applied to the memory cell;
monitoring a resistance of the memory cell to detect the memory cell temperature and leveling the current in response to the resistance reaching a desired value;
maintaining the current level for a set period to set the memory cell to the desired state; and
ramping down the current once the set period has elapsed.
15. The method of claim 14 , wherein applying the current to the memory cell comprises applying the current to the memory cell to reach a threshold voltage of the memory cell.
16. The method of claim 14 , wherein maintaining the current level for a set period comprises maintaining the current level for a crystallization time of the memory cell.
17. The method of claim 14 , wherein applying the current to the memory cell comprises applying the current to a bit line coupled to the memory cell, and wherein monitoring the resistance of the memory cell comprises determining the memory cell resistance based on the current and a bit line voltage.
18. The method of claim 14 , wherein applying the current to the memory cell comprises applying a first voltage to a bit line coupled to the memory cell and applying a second voltage to a word line of an access device coupled to the memory cell to provide the current, and wherein monitoring the resistance of the memory cell comprises determining the memory cell resistance based on the first voltage and the second voltage.
19. A method for programming a phase change memory cell, the method comprising:
resetting the memory cell to an amorphous state;
applying a current to the memory cell;
ramping up the current applied to the memory cell;
monitoring a voltage across the memory cell and leveling the current in response to the voltage and current reaching desired values indicating that the memory cell is at a desired temperature;
maintaining the current and voltage for a set period to set the memory cell to the desired state; and
ramping down the current once the set period has elapsed.
20. The method of claim 19 , wherein applying the current to the memory cell comprises applying the current to the memory cell to reach a threshold voltage of the memory cell.
21. The method of claim 19 , wherein maintaining the current and voltage for the set period comprises maintaining the current and voltage for a crystallization time of the memory cell.
22. The method of claim 19 , wherein applying the current to the memory cell comprises applying the current to a bit line coupled to the memory cell.
23. The method of claim 19 , wherein applying the current to the memory cell comprises applying a first voltage to a bit line coupled to the memory cell and applying a second voltage to a word line of an access device coupled to the memory cell to provide the current.