Buried bitline with reduced resistance
View Patent ↗A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.
1. A method of forming buried bitlines of a flash memory cell array, the method comprising:
providing a semiconductor substrate comprising a structure of a dielectric layer stack formed on a surface of the semiconductor substrate, a conductive layer formed on the dielectric layer stack, and a cap layer formed on the conductive layer;
forming trenches into the structure to expose part of the semiconductor substrate;
implanting dopants into the semiconductor substrate using a tilted implantation process to form pocket regions at opposing edges of the exposed part of the semiconductor substrate, wherein the pocket regions are non-overlapping with each other;
forming an insulating spacer structure covering sidewalls of the trenches, wherein the insulating spacer structure adjoins to a sidewall of the dielectric layer stack and to part of the semiconductor substrate, and wherein the pocket regions are formed prior to forming the insulating spacer structure;
after forming the insulating spacer structure, forming a doped semiconductor region within the exposed part of the semiconductor substrate;
forming a conductive region within the trenches on the doped semiconductor region, the conductive layer partially filling up the trenches; and
filling up the trenches with a dielectric material and removing the cap layer, part of the insulating spacer structure, and part of the dielectric material to expose the conductive layer.
2. The method according to claim 1 , wherein the conductive region within the trenches is formed up to a height that is below a top of the conductive layer.
3. The method according to claim 2 , wherein the conductive region within the trenches is formed up to a height that is below a top of the dielectric layer stack.
4. The method according to claim 2 , wherein the conductive region is formed by selective epitaxial growth.
5. The method according to claim 2 , wherein forming the conductive region comprises: filling up the trenches with a conductive material and implementing a recess etch, thereby removing part of the conductive material to provide the conductive region.
6. The method according to claim 1 , wherein the dielectric layer stack is formed as a stack comprising oxide/nitride/oxide layers.
7. The method according to claim 6 , wherein the doped semiconductor region is formed by implanting dopants.