Integrated circuit memory having a read circuit

1. A memory comprising:

a resistive memory cell; and

a circuit configured to provide an output signal indicating a state of the memory cell based on a comparison of a voltage across the memory cell to a threshold voltage,

wherein the circuit comprises:

a Schmitt-trigger comfigured to provide an output signal indicating a state of the memory cell based on a voltage across the memory cell;

a hold device configured to maintain the voltage across the memory cell at a voltage level indicating a low resistive state of the memory cell;

a bypass device configured to maintain the voltage across the memory cell at a voltage level indicating a high resistive state of the memory cell; and

a precharge circuit configured to precharge a bit line coupled to the memory cell.

2. The memory of claim 1 , wherein the memory cell comprises a phase-change memory cell.

3. The memory of claim 1 , wherein the memory cell comprises a magneto-resistive memory cell.

4. A method for determining a state of a memory cell, the method comprising:

precharging a bit line to a first voltage;

selecting a resistive memory cell to provide a second voltage on the bit line indicating a state of the memory cell;

comparing the second voltage to a threshold voltage; and

triggering an output signal indicating the state of the memory cell based on the comparison,

wherein the method comprises in response to a low resistive state of the memory cell providing a current on the bit line through a hold device to maintain the second voltage on the bit line at a voltage level indicating a low resistive state of the memory cell, and

wherein the method comprises in response to a high resistive state of the memory cell providing a current on the bit line through a bypass device to maintain the second voltage on the bit line at a voltage level indicating a high resistive state of the memory cell.

5. The method of claim 4 , wherein comparing the second voltage comprises comparing the second voltage to a threshold voltage in a Schmitt-trigger.

6. The method of claim 4 , wherein selecting the resistive memory cell comprises selecting a phase-change memory cell.

7. The method of claim 4 , wherein selecting the resistive memory cell comprises selecting one of a magneto-resistive memory cell and a conductive bridging memory cell.

8. The memory of claim 1 ,

wherein the resistive memory cell comprises a conductive bridging memory cell.