Method and apparatus for testing a memory chip using a common node for multiple inputs and outputs
View Patent ↗An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.
1. A method for testing an integrated device comprising memory, the method comprising:
providing a test device;
at least one of:
connecting N data inputs of the memory to a given data output of the test device, and
connecting N data outputs of the memory to a given data input of the test device, wherein N is an integer ≧2;
transferring test data from the test device to the memory and writing the transferred test data to memory cells of the memory;
reading data from memory cells of the memory and transferring the read data from the memory to the test device; and
comparing the data read from the memory with the test data written to the memory to identify faults of the memory.
2. The method as claimed in claim 1 , wherein N=2 X , and 1≦X≦6.
3. The method as claimed in claim 1 , in which at least two data outputs of the memory are coupled to a data input of the test device, wherein the step of comparing further comprises:
determining whether a signal level at the data input of the test device falls below a first predetermined threshold level;
determining whether the signal level at the data input of the test device exceeds a second predetermined threshold level;
diagnosing that a logic 0 is present at all the data outputs of the memory which are coupled to the data input of the test device when the signal level at the data input of the test device falls below the first predetermined threshold level; and
diagnosing that a logic 1 is present at all the data outputs of the memory which are coupled to the selected data input of the test device when the signal level at the data input of the test device exceeds the second predetermined threshold level.
4. The method as claimed in claim 3 , further comprising:
selecting a data output of the memory; and
turning off data outputs or output amplifiers of the memory which are not coupled to the selected data output of the memory.
5. A test device for testing a memory, the test device comprising:
a plurality of data outputs, wherein an output amplifier is associated with each of the plurality of data outputs,
a plurality of data inputs, wherein an input amplifier is associated with each of the plurality of data inputs, wherein at least one of:
each data input of the test device is coupled to a plurality of input terminals, wherein each of the plurality of input terminals is configured to be coupled to a respective data output of an integrated device comprising memory, and
each data output of the test device is coupled to a plurality of output terminals, wherein each of the plurality of output terminals is configured to be coupled to a respective data input of the integrated device comprising memory.