Processing arrangement, memory card device and method for operating and manufacturing a processing arrangement
View Patent ↗A processing arrangement ( 1 ) includes a processing unit ( 3 ) adapted to execute a predetermined set of processing instructions received from an instruction input ( 12 ). The set of processing instructions includes at least one predetermined processing instruction adapted to initiate a fixing operation. A memory unit ( 2 ) with a multiplicity of memory cells ( 5 ) is adapted to store data values. A detection unit ( 6 ) is adapted to detect a data value of a memory cell ( 5 ) and a data output ( 7 ) adapted to provide, on successful detection, the detected data value of a memory cell ( 5 ) or, on unsuccessful detection, a predetermined data value to the data output ( 7 ). The data output ( 7 ) is operationally coupled to the instruction input ( 12 ). The predetermined data value is mapped to the predetermined processing instruction adapted to initiate the fixing operation of an execution through the processing unit ( 3 ).
1. A processing arrangement comprising:
a processing unit adapted to execute a predetermined set of processing instructions received from an instruction input, the set of processing instructions comprising at least one predetermined processing instruction adapted to initiate a fixing operation;
a memory unit with a multiplicity of memory cells adapted to store data values;
a detection unit adapted to detect a data value of a memory cell; and
a data output adapted to provide, on successful detection, the detected data value of the memory cell, and on unsuccessful detection, a predetermined data value to the data output, the data output being operationally coupled to the instruction input, wherein the predetermined data value is mapped to the predetermined processing instruction adapted to initiate the fixing operation upon execution through the processing unit.
2. The processing arrangement according to claim 1 , wherein the predetermined processing instruction comprises a wait instruction, and the processing unit is configured to wait a predetermined amount of time on reception of the predetermined data value mapped to the wait instruction.
3. The processing arrangement according to claim 1 , wherein the predetermined processing instruction comprises a jump instruction and the processing unit is adapted to perform a jump to a predetermined address on reception of the predetermined data value mapped to the jump instruction.
4. The processing arrangement according to claim 1 , wherein the detection unit comprises a multiplicity of detectors and the fixing operation is adapted to test the functioning of at least one predetermined detector.
5. A processing arrangement comprising:
a memory unit; and
a processing unit operationally coupled to the memory unit, the memory unit being adapted to store processing instructions for the processing unit and to provide a predetermined data value to the processing unit if a processing instruction could not be retrieved from the memory unit, wherein the predetermined data value is mapped to a processing instruction causing the processing unit to initiate a fixing operation.
6. The processing arrangement according to claim 5 , wherein the fixing operation comprises a delay loop.
7. The processing arrangement according to claim 5 , wherein the memory unit comprises a non-volatile memory.
8. The processing arrangement according to claim 7 , wherein the memory unit comprises a first set of processing instructions adapted to perform the fixing operation if the processing instructions of the first set are executed by the processing unit.
9. The processing arrangement according to claim 8 , wherein the memory unit further comprises a second set of processing instructions adapted to perform a predetermined operation if the processing instructions of the second set are executed by the processing unit.
10. The processing arrangement according to claim 9 , wherein the first and second sets of processing instructions are interspersed.
11. A memory card device comprising:
an interface;
a processing unit; and
a non-volatile memory unit, the memory unit being operationally coupled to the interface by means of the processing unit,
wherein the memory unit is adapted to store processing instructions for the processing unit and to provide a predetermined data value to the processing unit if a processing instruction could not be retrieved from the memory unit, wherein the predetermined data value is mapped to a processing instruction causing the processing unit to initiate a fixing operation.
12. The memory card device according to claim 11 , wherein the fixing operation comprises a delay loop.
13. The memory card device according to claim 11 , wherein the memory unit comprises a first set of processing instructions adapted to perform the fixing operation if the processing instructions of the first set are executed by the processing unit.
14. The memory card device according to claim 13 , wherein the memory unit further comprises a second set of processing instructions adapted to perform a predetermined operation if the processing instructions of the second set are executed by the processing unit.
15. The memory card device according to claim 14 , wherein the first and second sets of processing instructions are interspersed.
16. A method for operating a processing arrangement that comprises a processing unit operationally coupled to a memory unit, the method comprising:
requesting a data value from the memory unit;
transmitting the requested data value from the memory unit to the processing unit when the requested data value can be retrieved from the memory unit;
transmitting a predetermined data value from the memory unit to the processing unit when the requested data value cannot be retrieved from the memory unit; and
performing a fixing operation by the processing unit upon reception of the predetermined data value.
17. The method according to claim 16 , wherein the predetermined data value is decoded as a jump instruction, and performing the fixing operation comprises requesting a processing instruction from a predetermined address comprised in the memory unit.
18. The method according to claim 16 , wherein the fixing operation comprises an initialization of the processing arrangement.
19. The method according to claim 16 , wherein the fixing operation comprises a recovery operation adapted to restore a state of the processing unit.
20. A method for forming a processing arrangement, the method comprising:
providing a set of processing instructions, at least one predetermined processing instruction being adapted to initiate a fixing operation;
providing a processing unit adapted to execute the set of processing instructions,
providing a memory unit adapted to store data values, the memory unit being adapted to transmit a data value stored in the memory unit when the data value can be retrieved from the memory unit and a predetermined data value, when the data value cannot be retrieved from the memory unit, to a data output; and
mapping the predetermined data value to the predetermined processing instructions adapted to initiate a fixing operation.
21. The method according to claim 20 , further comprising storing a first set of processing instructions adapted to perform the fixing operation in the memory unit.