IP Library Granted Patent US 7,615,444
Granted Patent B2
US 7,615,444 · App. 11/477,581 · Granted Nov 10, 2009

Method for forming a capacitor structure

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Quick Facts
Patent No.
US 7,615,444
App. No.
11/477,581
Granted
Nov 10, 2009
Kind
B2
Abstract

A method for forming a capacitor structure, according to which the following consecutive steps are executed: providing a substrate having on its surface contact pads and a dielectric mold provided with at least one trench leaving exposed the contact pads; forming a first conductive layer on side walls of the trench in a top region of the trench the conductive layer being without contact to the contact pads; depositing a first dielectric layer; depositing a second conductive layer on the contact pad and on the side walls of the trench; depositing a second dielectric layer; depositing a third conductive layer; and forming a vertical plug interconnecting the first conductive layer and the third conductive layer.

Claims (33)

1. A method for forming an integrated circuit having a capacitor structure:

providing a substrate having a contact pad and a dielectric mold thereover, the dielectric mold comprising at least one trench therein, thereby leaving exposed the contact pad;

forming a first conductive layer on side walls of the trench in a top region of the trench, the conductive layer not contacting the contact pad;

forming a first dielectric layer over the first conductive layer;

forming a second conductive layer on the contact pad, and on the side walls of the trench over the first dielectric layer;

forming a second dielectric layer over the second conductive layer;

forming a third conductive layer over the second dielectric layer; and

electrically connecting the first conductive layer and the third conductive layer, wherein the forming of the first conductive layer comprises:

depositing the first conductive layer;

depositing a masking layer over the first conductive layer selectively in the top region of the trench, thereby not overlying a bottom region of the trench;

etching the first conductive layer in the bottom region of the trench; and

removing the masking layer.

2. The method according to claim 1 , wherein the masking layer is formed by a chemical deposition method, at least one chemical reactant of the chemical deposition method having a concentration, which is decreased in the trench in a direction towards the contact pad and is approximately zero in the bottom region.

3. A method for forming an integrated circuit having a capacitor structure:

providing a substrate having a contact pad and a dielectric mold thereover, the dielectric mold comprising at least one trench therein, thereby leaving exposed the contact pad;

forming a first conductive layer on side walls of the trench in a top region of the trench, the conductive layer not contacting the contact pad;

forming a first dielectric layer over the first conductive layer;

forming a second conductive layer on the contact pad, and on the side walls of the trench over the first dielectric layer;

forming a second dielectric layer over the second conductive layer;

forming a third conductive layer over the second dielectric layer; and

electrically connecting the first conductive layer and the third conductive layer,

wherein before the first dielectric layer is formed, an isotropic etching step enlarges a diameter of a bottom region of the trench.

4. The method according to claim 3 , wherein the first conductive layer is formed by a chemical deposition method, at least one chemical reactant of the chemical deposition method having a concentration, which is decreasing in the trench in a direction towards the contact pad and is approximately zero in the bottom region.

5. The method according to claim 3 , wherein before the second conductive layer is deposited the following steps are executed:

forming a sacrificial layer over the first dielectric layer, the sacrificial layer having a first thickness above the contact pad in the trench and a second thickness above the dielectric mold outside the trench, the first thickness being smaller than the second thickness;

anisotropically etching the sacrificial layer until the sacrificial layer is removed above the contact pad, thereby exposing the first dielectric layer overlying the contact pad in the trench; and

selectively etching the exposed first dielectric layer, thereby exposing the contact pad.

6. The method according to claim 5 , wherein the sacrificial layer is formed by a chemical deposition method, at least one chemical reactant of the chemical deposition method having a concentration, which is decreasing in the trench in a direction towards the contact pad and is approximately zero in the bottom region.

7. The method according to claim 3 , wherein the second conductive layer is removed from a top surface of the dielectric mold outside the trench.

8. The method according to claim 7 , wherein the second conductive layer is removed by a chemical polishing method.

9. The method according to claim 3 , wherein before the second conductive layer is deposited a further dielectric mold having a further trench is formed on top of the dielectric mold, the further trench being arranged vertically in line to the trench.

10. The method of claim 3 , wherein electrically connecting the first and third conductive layers comprises forming a vertical conductive plug that interconnects the first and third conductive layers.

11. The method according to claim 10 , wherein the vertical plug is formed through a further dielectric mold for connecting the first conductive layer and the third conductive layer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037171/0719 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037147/0487 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2006
From: WUNNICKE, ODO; MOLL, PETER; SCHUPKE, KRISTIN
To: QIMONDA AG
Reel/Frame 018262/0975 →