Memory with an output register for test data and process for testing a memory and memory module

1. A memory, comprising:

a memory array comprising memory cells,

an input/output circuit which is connected to the memory cells and which interchanges data with the memory cells,

an output register which is connected to the input/output circuit, the output register being used to output data via a data output,

an input register which is connected to a data input and to the input/output circuit, the data input and the input register being used to input data into the memory cells, wherein test data is written to the output register in a test mode, wherein the output register is connected to the input register, wherein the output register forwards the test data to the input register in the test mode and the test data is transmitted from the input register to the input/output circuit, wherein the input/output circuit (i) writes the test data received from the input register to stipulated memory cells, (ii) reads the stipulated memory cells again and (iii) outputs them to the output register, wherein the output register supplies the data which have been read from the stipulated memory cells to the input register, and

an evaluation circuit connected to the input register, wherein the evaluation circuit checks the processing of the test data by the input/output circuit.

2. The memory as claimed in claim 1 , wherein the test data are read from the memory array by the input/output unit and are transmitted to the output register.

3. The memory as claimed in claim 1 , wherein the output register forwards the stored test data to the input register in cyclic succession in the test mode.

4. The memory as claimed in claim 1 , wherein the evaluation circuit compares the data from the stipulated memory cells with comparison data and outputs an error signal if there is a discrepancy.

5. The memory as claimed in claim 1 , wherein the evaluation circuit checks the data from the stipulated memory cells for a signature.

6. The memory as claimed in claim 1 , wherein the evaluation circuit is connected to an error register, and wherein the evaluation circuit stores an error data item in memory if a malfunction is identified.

7. The memory as claimed in claim 1 , wherein the memory is a synchronous memory which outputs the data from memory cells to the output register under the clocking of a clock signal, wherein the output register supplies the data to the input register in clocked fashion, and wherein the input register transfers the data to the input/output circuit in clocked fashion.

8. The memory as claimed in claim 7 , wherein the memory is in the form of a dynamic RAM store.

9. The memory as claimed in claim 1 , wherein the output register is in the form of a FIFO memory.

10. The memory as claimed in claim 9 , wherein the FIFO memory has an input pointer which takes a clock signal as a basis for connecting the input/output circuit to one of a plurality of data words, wherein the FIFO memory has an output pointer which connects one of the data words to an output of the FIFO memory, and wherein in the test mode the FIFO memory outputs the test data of the data words in cyclic succession.

11. The memory as claimed in claim 1 , wherein the output register is connected to the input register directly by means of data lines.

12. A process for testing a memory chip comprising (1) a memory array comprising memory cells, and (2) an input/output unit which is connected to an output register and to an input register, the process comprising:

writing test data from the input/output unit to the output register in a test mode,

forwarding the test data from the output register to the input register,

forwarding the test data from the input register to the input/output unit, wherein the test data is used by the input/output unit for a test process, and

checking result data which are obtained after the performance of the test process and which are forwarded from the input/output unit to the input register via the output register, wherein the checking is performed by an evaluation unit connected to the input register.

13. The process as claimed in claim 12 , wherein the test data are written to the output register when the test mode is started and are then routed in succession as a serial data stream to the input register.

14. A memory module, comprising:

a memory array comprising memory cells,

an input/output circuit which is connected to the memory cells and which interchanges data with the memory cells,

an output register which is connected to the input/output circuit, wherein the output register is used to output data via a data output,

an input register which is connected to a data input and to the input/output circuit, wherein the data input and the input register is used to input data into the memory cells, wherein test data is written to the output register in a test mode, wherein the output register is connected to the input register, wherein the output register forwards the test data to the input register in the test mode, the test data being transmitted from the input register to the input/output circuit, wherein the input/output circuit (i) writes the test data received from the input register to stipulated memory cells, (ii) reads the stipulated memory cells again and (iii) outputs them to the output register, wherein the output register supplies the data which have been read from the stipulated memory cells to the input register, and

an evaluation circuit connected to the input register, wherein the evaluation circuit checks the processing of the test data by the input/output circuit.

15. A computer system, comprising:

a memory array comprising memory cells,

an input/output circuit which is connected to the memory cells and which interchanges data with the memory cells,

an output register which is connected to the input/output circuit, with the output register being used to output data via a data output,

an input register which is connected to a data input and to the input/output circuit, wherein the data input and the input register are used to input data into the memory cells, where in test data being written to the output register in a test mode, wherein the output register is connected to the input register, wherein the output register forwards the test data to the input register in the test mode, the test data being transmitted from the input register to the input/output circuit, wherein the input/output circuit (i) writes the test data received from the input register to stipulated memory cells, (ii) reads the stipulated memory cells again and (iii) outputs them to the output register, wherein the output register supplies the data which have been read from the stipulated memory cells to the input register, and

an evaluation circuit connected to the input register, wherein the evaluation circuit checks the processing of the test data by the input/output circuit.