Memory element with positive temperature coefficient layer

1. An integrated circuit comprising:

a memory element that comprises a top contact, a bottom contact, a switching layer disposed between the top contact and the bottom contact, and a positive temperature coefficient layer in thermal contact with the switching layer,

wherein the switching layer selectively switches between a low resistance state and a high resistance state, wherein the switching layer comprises a transition metal oxide material, wherein the transition metal oxide material comprises NiO 1-x , where x is in the range of approximately 0.01 to approximately 0.15; and

wherein a resistance of the positive temperature coefficient layer increases in response to an increase in temperature.

2. The integrated circuit of claim 1 , wherein the switching layer comprises a bistable switching material.

3. The integrated circuit of claim 1 , wherein the positive temperature coefficient layer is electrically connected in series with the switching layer.

4. The integrated circuit of claim 1 , wherein the positive temperature coefficient layer comprises at least one of BaTiO 3 , TiO 3 , and/or a Ba x Sr 1-x compound.

5. The integrated circuit of claim 1 , wherein the switching layer switches between the high resistance state and the low resistance state by forming a conductive filament within the switching layer.

6. The integrated circuit of claim 5 , wherein the positive temperature coefficient layer limits a current density in the conductive filament.

7. The integrated circuit of claim 1 , wherein the positive temperature coefficient layer increases a number of switching cycles of the memory element.

8. A method of manufacturing an integrated circuit, the method comprising:

depositing a switching layer material above a substrate, the switching layer material being capable of selectively switching between a low resistance state and a high resistance state, wherein the switching layer comprises a transition metal oxide material, wherein the transition metal oxide material comprises NiO 1-x , where x is in the range of approximately 0.01 to approximately 0.15; and

depositing a positive temperature coefficient material in thermal contact with the switching layer material, the positive temperature coefficient material having a resistance that increases in response to an increase in temperature.

9. The method of claim 8 , wherein depositing the positive temperature coefficient material comprises a material comprising at least one of BaTiO 3 , TiO 3 , and/or a Ba x Sr 1-x compound.

10. The method of claim 8 , wherein depositing the switching layer material comprises depositing a layer of the switching layer material having a thickness in the range of approximately 20 nm to approximately 50 nm.

11. The method of claim 8 , wherein depositing the positive temperature coefficient material comprises depositing a layer of the positive temperature coefficient material having a thickness in the range of approximately 30 nm to approximately 50 nm.

12. An integrated circuit comprising:

a memory cell that comprises a select transistor and a memory element coupled to the select transistor, the memory element comprising a switching layer and a positive temperature coefficient layer in thermal contact with the switching layer;

wherein a resistance of the positive temperature coefficient layer increases in response to an increase in temperature;

wherein the switching layer comprises a transition metal oxide material, wherein the transition metal oxide material comprises NiO 1-x , where x is in the range of approximately 0.01 to approximately 0.15; and

wherein information is stored by selectively switching the switching layer between a low resistance state and a high resistance state.

13. The integrated circuit of claim 12 , wherein the positive temperature coefficient layer is electrically connected in series with the switching layer.

14. The integrated circuit of claim 12 , wherein the switching layer switches between the high resistance state and the low resistance state by forming a conductive filament within the switching layer.

15. The integrated circuit of claim 14 , wherein the positive temperature coefficient layer limits a current density in the conductive filament.

16. A method for storing information, the method comprising:

providing a memory element comprising a switching layer and a positive temperature coefficient layer adjacent the switching layer,

wherein the switching layer comprises a transition metal oxide material, wherein the transition metal oxide material comprises NiO 1-x , where x is in the range of approximately 0.01 to approximately 0.15,

wherein a resistance of the positive temperature coefficient layer increases in response to an increase in temperature; and

selectively switching the memory element between a low resistance state and a high resistance state to store information.

17. The method of claim 16 , wherein providing the memory element comprises electrically connecting the positive temperature coefficient layer in series with the switching layer.

18. A memory module comprising:

a plurality of integrated circuits, wherein each integrated circuit comprises a resistive memory element comprising a switching layer and a positive temperature coefficient layer in thermal contact with the switching layer, wherein the switching layer selectively switches between a low resistance state and a high resistance state; and wherein a resistance of the positive temperature coefficient layer increases in response to an increase in temperature; wherein the switching layer comprises a transition metal oxide material, wherein the transition metal oxide material comprises NiO 1-x , where x is in the range of approximately 0.01 to approximately 0.15; and wherein the integrated circuits are electrically coupled together to form a module.

19. The memory module of claim 18 , wherein the memory module is stackable.