Thermal isolation of phase change memory cells

1. A memory comprising:

an array of resistive memory cells arranged in rows and columns;

bit lines coupled to each of the memory cells; and

a conductive perforated plate laterally surrounding the memory cells for accessing the memory cells, the conductive perforated plate arranged over a plurality of rows and over a plurality of columns of the memory cells.

2. The memory of claim 1 , wherein the conductive plate comprises a ground plate.

3. The memory of claim 1 , wherein the memory cells comprise phase-change memory cells.

4. The memory of claim 1 , wherein the conductive plate is below the bit lines.

5. The memory of claim 1 , further comprising:

word lines substantially perpendicular to the bit lines, each word line for controlling a transistor having a source-drain path coupled between the conductive plate and a memory element.

6. The memory of claim 1 , wherein the conductive plate thermally isolates the memory cells.

7. An integrated circuit comprising:

an array of resistive memory cells, each memory cell including a transistor and a memory element;

bit lines coupled to each of the memory cells;

a plurality of electrodes, each electrode coupled to a memory cell; and

a around plate directly coupled to each of the electrodes within at least two rows and at least two columns of the memory cells, the ground plate arranged above the plurality of electrodes and above a plurality of rows and above a plurality of columns of the transistors,

wherein the bit lines are above the ground plate and the ground plate is perforated.

8. The integrated circuit of claim 7 , wherein the array of memory cells comprises an array of single gate memory cells.

9. An integrated circuit comprising:

an array of resistive memory cells, each memory cell including a transistor and a memory element;

bit lines coupled to each of the memory cells;

a plurality of electrodes, each electrode coupled to a memory cell; and

a ground plate directly coupled to each of the electrodes within at least two rows and at least two columns of the memory cells, the around plate arranged above the plurality of electrodes and above a plurality of rows and above a plurality of columns of the transistors,

wherein the array of memory cells comprises an array of dual gate memory cells.

10. The integrated circuit of claim 9 , wherein the bit lines are below the ground plate.

11. The integrated circuit of claim 9 , wherein the bit lines thermally isolate the memory cells.

12. The integrated circuit of claim 9 , wherein the ground plate thermally isolates the memory cells.

13. A method for fabricating a memory, the method comprising:

providing an array of resistive memory cells arranged in rows and columns;

providing bit lines coupled to each of the memory cells; and

providing a perforated conductive plate laterally surrounding the memory cells for accessing the memory cells, the perforated conductive plate arranged over a plurality of rows and over a plurality of columns of the memory cells.

14. The method of claim 13 , wherein providing the array of memory cells comprises providing an array of phase-change memory cells.

15. The method of claim 13 , further comprising:

providing word lines substantially perpendicular to the bit lines, each word line for controlling a transistor having a source-drain path coupled between a memory element and the conductive plate.

16. The method of claim 13 , wherein providing the conductive plate comprises providing the conductive plate for thermally isolating the memory cells.