Arrangement of semiconductor memory devices and semiconductor memory module comprising an arrangement of semiconductor memory devices

1. An arrangement of semiconductor memory devices, the arrangement comprising:

a first semiconductor memory device having an underside, at least one first contact being provided on a first section of the underside of the first semiconductor memory device, and at least one second contact being provided on a second section of the underside of the first semiconductor memory device;

a second semiconductor memory device having an underside, at least one first contact being provided on a first section of the underside of the second semiconductor memory device, and at least one second contact being provided on a second section of the underside of the second semiconductor memory device;

a flexible substrate having an underside, the flexible substrate having a first section and a second section, at least one first contact being arranged on the underside of the first section of the flexible substrate and at least one second contact being arranged on the underside of the second section of the flexible substrate;

the first semiconductor memory device being arranged on the first and second sections of the flexible substrate, and the second semiconductor memory device being arranged on the first semiconductor memory device;

a first electrically conductive conductor track arranged in the flexible substrate, the at least one first contact of the flexible substrate being coupled to the at least one second contact of the second semiconductor memory device through the first electrically conductive conductor track;

a second electrically conductive conductor track, arranged in the flexible substrate, the at least one first contact of the second semiconductor memory device is coupled to the at least one second contact of the first semiconductor memory device through the second electrically conductive conductor track; and

a third electrically conductive conductor track, arranged in the flexible substrates, the third electrically conductive conductor track comprising a plated-through hole section, said plated-through hole section formed through the flexible substrate, the at least one first contact of the first semiconductor memory device is coupled to the at least one second contact of the flexible substrate through the third electrically conductive conductor track.

2. The arrangement of semiconductor memory devices as claimed in claim 1 , wherein the flexible substrate has a top side, and the underside of the first semiconductor memory device is arranged on the top side of the first and second sections of the flexible substrate.

3. The arrangement of semiconductor memory devices as claimed in claim 1 , wherein the first semiconductor memory device has a top side and the second semiconductor memory device has a top side, and the top side of the first semiconductor memory device faces the top side of the second semiconductor memory device.

4. The arrangement of semiconductor memory devices as claimed in claim 3 , wherein an adhesion agent is provided between the top side of the first semiconductor memory device and the top side of the second semiconductor memory device.

5. The arrangement of semiconductor memory devices as claimed in claim 1 , wherein the flexible substrate comprises a third section adjacent to the first section, an end section of the third section of the flexible substrate having at least one connection contact through which the first electrically conductive conductor track is coupled to the at least one second contact of the second semiconductor memory device.

6. The arrangement of semiconductor memory devices as claimed in claim 5 , wherein the top side of the end section of the third section of the flexible substrate faces the underside of the second section of the second semiconductor memory device.

7. The arrangement of semiconductor memory devices as claimed in claim 6 , wherein the at least one connection contact of the end section of the third section of the flexible substrate is arranged on the top side of the end section of the third section of the flexible substrate.

8. The arrangement of semiconductor memory devices as claimed in claim 1 , wherein the flexible substrate comprises a third section adjacent to the first section, and a fourth section adjacent to the second section, an end section of the fourth section of the flexible substrate having at least one connection contact through which the second electrically conductive conductor track is connected to the at least one first contact of the second semiconductor device.

9. The arrangement of semiconductor memory devices as claimed in claim 8 , wherein the top side of the end section of the fourth section of the flexible substrate faces the underside of the first section of the second semiconductor memory device.

10. The arrangement of semiconductor memory devices as claimed in claim 1 , wherein at least one connection contact by which the third electrically conductive conductor track is coupled to the at least one first contact of the second semiconductor memory device is provided on the top side of the first section of the flexible substrate.

11. The arrangement of semiconductor memory devices as claimed in claim 1 , wherein at least one connection contact by which the second electrically conductive conductor track is coupled to the at least one first contact of the second semiconductor memory device is provided on the top side of the second section of the flexible substrate.

12. The arrangement of semiconductor memory devices as claimed in claim 5 , wherein the third section of the flexible substrate has a first and a second partial section and in which the first electrically conductive conductor track has a first section and a second section and the first section of the first electrically conductive conductor track is arranged on the underside of the first partial section of the third section of the flexible substrate.

13. The arrangement of semiconductor memory devices as claimed in claim 12 , wherein the second section of the first electrically conductive conductor track is arranged on the top side of the second partial section of the third section of the flexible substrate.

14. The arrangement of semiconductor memory devices as claimed in claim 13 , wherein the first electrically conductive conductor track has a third section, through which the first section is coupled to the second section of the electrically conductive conductor track.

15. The arrangement of semiconductor memory devices as claimed in claim 8 , wherein the second electrically conductive conductor track is arranged on the top side of the fourth section of the flexible substrate.

16. The arrangement of semiconductor memory devices as claimed in claim 1 , wherein the third electrically conductive conductor track has a first section and a second section, the first section of the third electrically conductive conductor track being arranged on the top side of the first section of the flexible substrate, and the second section of the third electrically conductive conductor track being arranged on the underside of the second section of the flexible substrate.

17. The arrangement of semiconductor memory devices as claimed in claim 16 , wherein the first section of the third electrically conductive conductor track is coupled to the second section of the third electrically conductive conductor track by the plated-through hole section.

18. The arrangement of semiconductor memory devices as claimed in claim 1 , wherein the first and the second semiconductor memory device each comprise at least one integrated semiconductor component.

19. The arrangement of semiconductor memory devices as claimed in claim 18 , wherein the integrated semiconductor component comprises dynamic random access memory cells.

20. The arrangement of semiconductor memory devices as claimed in claim 2 , wherein a filler material is provided between the top side of the flexible substrate and the underside of the first semiconductor memory device.