Method for manufacturing a structure in a semiconductor device and a structure in a semiconductor device

1. Method for manufacturing a local wiring in a semiconductor device, comprising manufacturing at least two electrically conducting structures essentially in the same horizontal level in a layered stack on a substrate, the at least two electrically conducting structures being separated by a gap filled with at least one dielectric material, the gap being electrically bridged by conductive material, to form at least one contact element electrically connecting the at least two electrically conducting structures, whereby the at least one contact element is produced in a single lithographic step, wherein the at least one contact element is positioned by filling a hole with electrically conducting material.

2. Method according to claim 1 , wherein the at least one contact element is deposited in a first layer and the at least two electrically conducting structures are deposited in a level above the first layer.

3. Method according to claim 1 , wherein at least a first contact element is manufactured in a first layer, the at least two electrically conducting structures are manufactured in a level above the first layer and at least a second contact element is manufactured in a second layer above the at least two electrically conducting structures.

4. Method according to claim 1 , wherein the at least one contact element is manufactured in a second layer, the at least two electrically conducting structures are manufactured in a level below the second layer.

5. Method according to claim 1 , wherein the at least one dielectric material comprises a line-spacer element, a silicon oxide structure, a SiO x N y structure, a SiN x structure or an airfilled space.

6. Method according to claim 5 , wherein the at least one dielectric material is produced by a line-by-spacer method, a line-shrink method, a space-shrink method or an electron beam processing.

7. Method according to claim 1 , wherein the at least one contact element comprises a round patch with the at least two electrically conducting structures overlapping the patch.

8. Method according to claim 1 , wherein the at least one contact element comprises a polygonal patch with the at least two electrically conducting structures overlapping the patch.

9. Method according to claim 1 , wherein the at least two electrically conducting structures are line structures.

10. Method according to claim 1 , wherein the at least two electrically conducting structures are part of the same metallization layer.

11. Method according to claim 1 , wherein at least one of the electrically conducting structures comprises tungsten, cobalt, aluminum and/or copper.

12. Method according to claim 1 , wherein at least one of the electrically conducting structures is manufactured by a pitch fragmentation method.

13. Method according to claim 1 , wherein the at least two electrically conducting structures are part of a DRAM layout.

14. Structure in a local wiring in a semiconductor device, obtained by manufacturing of at least two electrically conducting structures essentially in the same horizontal level in a layered stack on a substrate, the at least two electrically conducting structures being separated by a gap filled with at least one dielectric material, the gap manufactured in one lithography step, the gap electrically bridged with conductive material, to form at least one contact element electrically connecting the at least two electrically conducting structures, whereby at least one contact element is produced in a single lithographic step, wherein the at least one contact element comprises a round patch with the at least two electrically conducting structures overlapping the patch.

15. Structure according to claim 14 , wherein the at least one contact element lies in a first layer and the at least two electrically conducting structures are lying in a level above the first layer.

16. Structure according to claim 14 , wherein the at least one contact element lies in a second layer and the at least two electrically conducting structures are lying in a level under the second layer.

17. Structure according to claim 14 , wherein at least a first contact element lies in a first layer, the at least two electrically conducting structures are lying in a level above the first layer and at least a second contact element is lying in a second layer above the at least two electrically conducting structures.

18. Structure according to claim 14 , wherein the at least one contact element is fully embedded into dielectric material.

19. Structure according to claim 14 , wherein the at least one dielectric material comprises a line-spacer element, sublithographic structure, a silicon oxide structure, a SiO x N y structure, a SiN x structure and/or an airfilled space.

20. Structure according to claim 14 , wherein the at least one contact element comprises a polygonal patch with the at least two electrically conducting structures overlapping the patch.

21. Structure according to claim 14 , wherein the at least two electrically conducting structures are part of the same metallization layer.

22. Structure according to claim 14 , wherein at least one electrically conducting structure comprises tungsten, cobalt or aluminum.

23. Method for manufacturing a local wiring in a semiconductor device, comprising manufacturing at least two electrically conducting structures essentially in the same horizontal level in a layered stack on a substrate, the at least two electrically conducting structures being separated by a gap filled with at least one dielectric material, the gap being electrically bridged by conductive material, to form at least one contact element electrically connecting the at least two electrically conducting structures, whereby at least one contact element is produced in a single lithographic step, wherein the at least one contact element comprises a round patch with the at least two electrically conducting structures overlapping the patch.