Phase change random access memory device with transistor, and method for fabricating a memory device

1. An integrated circuit comprising:

an array of memory cells;

wherein each memory cell comprises a volume of switching active material and a selection element;

said volume of switching active material being contacted by a first end of a nanotube, the nanotube having a ring-shaped contact formed around a non-conducting nanowire;

wherein the material of the nanotube is a metal;

wherein the switching active material is a phase change material; and

wherein the selection element is provided with at least one source/drain contact, an upper surface of the at least one source/drain contact is disposed with a silicon contact, and the selection element is further provided with at least one spacer such that the upper surface of the at least one source/drain contact, the silicon contact, and the at least one spacer defines a chasm; wherein a second end of the nanotube fills the chasm and surrounds the silicon contact, thereby forming a good electrical connection between the nanotube and the selection element.

2. The integrated circuit of claim 1 , wherein the ring-shaped contact is formed as a spacer around the nanowire.

3. The integrated circuit of claim 1 , wherein the thickness of the ring-shaped contact is less than 10 nanometers.

4. The integrated circuit of claim 3 , wherein the thickness of the ring-shaped contact is less than 2 nanometers.

5. The integrated circuit of claim 1 , wherein the material of the ring-shaped contact is titanium nitride.

6. The integrated circuit of claim 1 , wherein the inner diameter of the ring-shaped contact is equal to or less than 65 nanometers.

7. An integrated circuit comprising:

a plurality of memory cells;

each memory cell comprising a volume of switching active material, a selection element, and a nanotube of conducting material formed as a layer of conducting material surrounding a nanowire of non-conducting material;

wherein the volume of switching active material is coupled to the selection element via the nanotube;

wherein a first ring-shaped front face of the nanotube forms a contact to the volume of switching active material;

wherein the material of the first ring-shaped front face is a metal;

wherein the switching active material is a phase change material;

wherein the selection element and a spacer define a chasm such that the nanotube substantially fills the chasm thereby forming good electrical connection between the selection element and a second end of the nanotube; and

wherein at the second end of the nanotube the outer diameter of the nanotube decreases.

8. The integrated circuit of claim 7 , wherein the second end of the nanotube is coupled to another conductor.

9. The integrated circuit of claim 8 , wherein the second end of the nanotube is coupled at its inner side to the drain of the selection element.

10. The integrated circuit of claim 7 , wherein the layer of conducting material is formed as a spacer around the nanowire.

11. The integrated circuit of claim 7 , wherein the conducting material of the nanotube is titanium nitride (TiN).

12. The integrated circuit of claim 7 , wherein the non-conducting material of the nanowire is intrinsic silicon.

13. The integrated circuit of claim 7 , wherein the inner diameter of the nanotube is less than 30 nanometers.

14. The integrated circuit of claim 7 , wherein the thickness of the wall of the nanotube is less than 10 nanometers, preferably less than 2 nanometers.

15. The integrated circuit of claim 7 , wherein the length of the nanotube is between 50 and 200 nanometers.

16. An integrated circuit with a plurality of memory cells formed on a wafer, wherein the surface of the original wafer serves as a horizontal reference plane, and wherein each of the memory cells comprises:

a volume of switching active material;

a selection element for selecting a memory cell from the plurality of memory cells; and

a nanotube of conducting material for connecting the volume of switching active material, the rotation axis of the nanotube being perpendicular to the reference plane, the nanotube formed as a layer of conducting material surrounding a nanowire of non-conducting material;

wherein a ring-shaped front face at a first end of the nanotube forms a metal contact to the volume of switching active material;

wherein the switching active material is a phase change material; and

wherein the selection element is provided with at least one source/drain contact, an upper surface of the at least one source/drain contact is disposed with a silicon contact, and the selection element is further provided with at least one spacer such that the upper surface of the at least one source/drain contact, the silicon contact, and the at least one spacer defines a chasm; wherein a second end of the nanotube fills the chasm and surrounds the silicon contact, thereby forming a good electrical connection between the nanotube and the selection element.

17. The integrated circuit of claim 16 , wherein the front face of the nanotube forms a bottom electrode contact of the volume of switching active material.

18. The integrated circuit of claim 16 , wherein the volume of the switching active material is coupled to the selection element via the nanotube.

19. The integrated circuit of claim 16 , wherein the nanotube is contacted at its inside at the opposite end of that coupled to the volume of switching active material.

20. The integrated circuit of claim 16 , wherein the inner diameter of the nanotube is less than 30 nanometers.

21. The integrated circuit of claim 16 , wherein the thickness of the wall of the nanotube is less than 10 nanometers, preferably less than 2 nanometers.

22. The integrated circuit of claim 16 , wherein the nanotube is coupled with a second end to a drain of the selection element.

23. The integrated circuit of claim 16 , wherein the material of the nanotube is titanium nitride.

24. The integrated circuit of claim 16 , wherein the switching active material is phase change material.

25. An electronic system, comprising the integrated circuit of claim 1 .