Programmable resistive memory cell with a programmable resistance layer
View Patent ↗A programmable resistive memory cell comprising a lower electrode, a programmable resistance layer, and an upper electrode, wherein a lower mask is arranged between the lower electrode and the programmable resistance layer and an upper mask is arranged between the programmable resistance layer and the upper electrode, and wherein the lower mask and the upper mask comprise current-inhibiting regions.
1. A programmable resistive memory cell, comprising:
a lower electrode;
a programmable resistance layer; and
an upper electrode,
wherein a lower mask is arranged between the lower electrode and the programmable resistance layer and an upper mask is arranged between the programmable resistance layer and the upper electrode, and the lower mask and the upper mask comprise current-inhibiting regions,
wherein at least two separate contact areas between the lower electrode and the programmable resistance layer are formed by the current-inhibiting regions of the lower mask.
2. The memory cell as claimed in claim 1 , wherein the current-inhibiting regions comprise an insulator.
3. The memory cell as claimed in claim 2 , wherein the current-inhibiting regions comprise a metal oxide.
4. The memory cell as claimed in claim 3 , wherein the current inhibiting regions comprise zinc oxide.
5. The memory cell as claimed in claim 1 , wherein a lateral extent of the current-inhibiting regions is in a range of 2 to 20 nm.
6. The memory cell as claimed in claim 1 , wherein open regions are arranged between two adjacent current-inhibiting regions, and the open regions have a lateral extent in a range of 2 to 20 nm.
7. The memory cell as claimed in claim 1 , wherein a layer thickness of the lower mask and of the upper mask are in a range of 1 to 10 nm.
8. The memory cell as claimed in claim 1 , wherein the lower mask is arranged such that it adjoins the lower electrode on an underside and elsewhere adjoins the programmable resistance layer.
9. The memory cell as claimed in claim 1 , wherein the upper mask is arranged such that it adjoins the programmable resistance layer on an underside and elsewhere adjoins the upper electrode.
10. The memory cell as claimed in claim 1 , wherein the programmable resistance layer comprises a transition metal oxide.
11. The memory cell as claimed in claim 10 , wherein the programmable resistance layer comprises a further transition metal oxide.
12. The memory cell as claimed in claim 10 , wherein at least one of the transition metals niobium, titanium, nickel, zirconium, chromium, cobalt, manganese, vanadium, tantalum, hafnium, or iron forms an oxide.
13. The memory cell as claimed in claim 10 , wherein the programmable resistance layer comprises at least one of the metals strontium, lead, praseodymium or calcium.
14. The memory cell as claimed in claim 1 , wherein the programmable resistance layer is surrounded by an insulating layer.
15. The memory cell as claimed in claim 1 , wherein the lower electrode and the upper electrode comprise at least one of the metals tungsten, platinum or palladium.
16. A programmable resistive memory cell, comprising:
a lower electrode;
a contact;
a programmable resistance layer; and
an upper electrode,
wherein a lower mask is arranged between the contact and the programmable resistance layer, the lower mask comprises current-inhibiting regions, the contact is arranged between the lower electrode and the lower mask, and the contact being surrounded by an insulating contact mold layer; and
wherein the contact is tapered downward.
17. The memory cell as claimed in claim 16 , wherein an upper mask is arranged between the programmable resistance layer and the upper electrode.
18. A programmable resistive memory cell, comprising:
a lower electrode;
a programmable resistance layer; and
an upper electrode,
wherein a lower mask is arranged between the lower electrode and the programmable resistance layer and an upper mask is arranged between the programmable resistance layer and the upper electrode, and the lower mask and the upper mask comprise current-inhibiting regions, the current-inhibiting regions each comprising at least one nanoparticle, the lateral extent of the nanoparticles being in a range of 2 to 20 nm.
19. The memory cell as claimed in claim 18 , wherein the nanoparticles comprise a metal oxide.
20. The memory cell as claimed in claim 19 , wherein the nanoparticles comprise zinc oxide.
21. A programmable resistive memory cell, comprising:
a lower electrode;
a programmable resistance layer; and
an upper electrode,
wherein a lower mask is arranged between the lower electrode and the programmable resistance layer and an upper mask is arranged between the programmable resistance layer and the upper electrode, and the lower mask and the upper mask comprise current-inhibiting regions, and
wherein the current-inhibiting regions comprise an insulator comprising a metal oxide.
22. The memory cell as claimed in claim 21 , wherein the current inhibiting regions comprise zinc oxide.