IP Library › Assignment 023768/0001
Patent Assignment
Reel/Frame 023768/0001

ASSIGNMENT OF ASSIGNOR'S INTEREST

Recorded: 2010-01-12 Received: 2010-01-12 Pages: 396
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2006-04-25
Assignee
QIMONDA AG
GUSTAV-HEINEMANN-RING 212, MUNICH, DEX, 81739, GERMANY
Covered Applications (100)
CACHE MANAGEMENT SYSTEM
App. No. 12/634,397
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INFORMATION RETRIEVAL FROM A COLLECTION OF INFORMATION OBJECTS TAGGED WITH HIERARCHICAL KEYWORDS
App. No. 12/628,132
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METHOD AND SYSTEM FOR DETECTING GAPS IN A DATA STREAM
App. No. 12/614,182
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SEMICONDUCTOR DEVICE WITH PLASTIC PACKAGE MOLDING COMPOUND, SEMICONDUCTOR CHIP AND LEADFRAME AND METHOD FOR PRODUCING THE SAME
App. No. 10/577,173
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METHOD AND SYSTEM FOR MESSAGE PACING
App. No. 12/566,364
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METHOD AND COMPUTER SYSTEM FOR UNSTRUCTURED DATA INTEGRATION THROUGH GRAPHICAL INTERFACE
App. No. 12/547,962
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METHOD AND SYSTEM FOR FACILITATING MARKETING DIALOGUES
App. No. 12/546,981
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METHOD AND SYSTEM FOR FACILITATING MARKETING DIALOGUES
App. No. 12/546,220
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SYSTEM AND METHOD FOR THE SYNCHRONIZATION OF A FILE IN A CACHE
App. No. 12/545,423
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SYSTEM AND METHOD OF ASSOCIATING EVENTS WITH REQUESTS
App. No. 12/545,412
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OBJECT STRUCTURE-BASED SYSTEM AND METHOD FOR MANAGING INFORMATION
App. No. 12/545,384
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METHOD AND SYSTEM FOR PERFORMING BULK OPERATIONS ON TRANSACTIONAL ITEMS
App. No. 12/272,139
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METHOD AND SYSTEM FOR IDENTIFYING WEBSITE VISITORS
App. No. 12/266,129
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CONTEXTUAL REGENERATION OF PAGES FOR WEB-BASED APPLICATIONS
App. No. 12/212,414
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EVENT-DRIVEN REGENERATION OF PAGES FOR WEB-BASED APPLICATIONS
App. No. 12/208,934
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SYSTEM AND METHOD FOR MANAGING PAGE VARIATIONS IN A PAGE DELIVERY CACHE
App. No. 12/208,072
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SYSTEM AND METHOD FOR MANAGING LARGE FILESYSTEM-BASED CACHES
App. No. 12/206,909
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INTEGRATED CIRCUIT WITH MEMORY HAVING A CURRENT LIMITING SWITCH
App. No. 12/206,378
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METHOD FOR PRODUCING A DIELECTRIC INTERLAYER AND STORAGE CAPACITOR WITH SUCH A DIELECTRIC INTERLAYER
App. No. 12/198,005
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INTEGRATED CIRCUIT COMPRISING AN ORGANIC SEMICONDUCTOR, AND METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT
App. No. 12/188,966
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SIGNAL ROUTING ON REDISTRIBUTION LAYER
App. No. 12/123,701
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METHOD FOR PRODUCING A STRUCTURE ON THE SURFACE OF A SUBSTRATE
App. No. 12/114,948
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SEMICONDUCTOR MEMORY HAVING CHARGE TRAPPING MEMORY CELLS AND FABRICATION METHOD THEREOF
App. No. 12/110,849
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EUV Lithography System and Chuck for Releasing Reticle in a Vacuum Isolated Environment
App. No. 12/110,062
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METHOD OF FABRICATING AN INTEGRATED CIRCUIT HAVING A MEMORY INCLUDING A LOW-K DIELECTRIC MATERIAL
App. No. 12/050,727
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MEMORY DEVICE
App. No. 12/049,484
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TRANSISTOR ARRAY FOR SEMICONDUCTOR MEMORY DEVICES AND METHOD FOR FABRICATING A VERTICAL CHANNEL TRANSISTOR ARRAY
App. No. 12/042,822
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Method and System for Modeling of System Content for Businesses
App. No. 12/023,733
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INTEGRATED CIRCUIT INCLUDING A MEMORY FABRICATED USING SELF-ALIGNED PROCESSING
App. No. 12/020,988
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STACKED DIE PACKAGE
App. No. 12/014,632
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ENERGY ADJUSTED WRITE PULSES IN PHASE-CHANGE MEMORY CELLS
App. No. 11/972,415
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METHOD OF FORMING AN INTEGRATED CIRCUIT INCLUDING A TRANSISTOR
App. No. 11/963,044
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HIGH DIELECTRIC CONSTANT MATERIALS
App. No. 11/961,769
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MEMORY CELL ARRAY
App. No. 11/945,437
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METHOD FOR FABRICATING METALLIC BIT-LINE CONTACTS
App. No. 11/929,215
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INTEGRATED CIRCUIT INCLUDING A GATE ELECTRODE
App. No. 11/926,653
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VOLTAGE REGULATION SYSTEM
App. No. 10/585,151
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CACHE MANAGEMENT SYSTEM WITH APPLICATION-INDEPENDENT POLLING
App. No. 11/871,862
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TEMPERATURE UPDATE MASKING TO ENSURE CORRECT MEASUREMENT OF TEMPERATURE WHEN REFERENCES BECOME UNSTABLE
App. No. 11/868,928
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MEMORY SYSTEM AND METHOD FOR TRANSFERRING DATA THEREIN
App. No. 11/862,915
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IMPLEMENTATION OF A FUSING SCHEME TO ALLOW INTERNAL VOLTAGE TRIMMING
App. No. 11/860,332
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TRANSACTION MANAGEMENT SYSTEM
App. No. 11/903,373
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STORAGE CAPACITOR AND METHOD OF MANUFACTURING A STORAGE CAPACITOR
App. No. 11/856,409
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FIELD-EFFECT TRANSISTOR STRUCTURES WITH GATE ELECTRODES WITH A METAL LAYER
App. No. 11/849,727
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Integrated Circuit Including a Memory Cell Array
App. No. 11/844,853
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METHOD AND SYSTEM FOR CACHE MANAGEMENT
App. No. 11/825,909
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MRAM MEMORY CELL HAVING A WEAK INTRINSIC ANISOTROPIC STORAGE LAYER AND METHOD OF PRODUCING THE SAME
App. No. 11/769,454
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METHOD AND SYSTEM FOR FACILITATING MARKETING DIALOGUES
App. No. 11/818,192
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SEMICONDUCTOR MEMORY CHIP
App. No. 11/751,984
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CIRCUIT AND METHOD FOR ADJUSTING THRESHOLD DRIFT OVER TEMPERATURE IN A CMOS RECEIVER
App. No. 11/804,092
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Method for Automatically Generating at Least One of a Mask Layout and an Illumination Pixel Pattern of an Imaging System
App. No. 11/740,150
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PHASE CHANGE MEMORY CELL WITH HIGH READ MARGIN AT LOW POWER OPERATION
App. No. 11/737,838
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PHASE CHANGE MEMORY CELL WITH HIGH READ MARGIN AT LOW POWER OPERATION
App. No. 11/737,847
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METHOD FOR CLEANING A SEMICONDUCTOR WAFER
App. No. 11/697,883
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METHOD FOR CLICK-STREAM ANALYSIS USING WEB DIRECTORY REVERSE CATEGORIZATION
App. No. 11/729,530
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METHOD FOR CLASSIFYING ERRORS IN THE LAYOUT OF A SEMICONDUCTOR CIRCUIT
App. No. 11/712,635
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SYSTEM AND METHOD FOR TESTING ONE OR MORE DIES ON A SEMICONDUCTOR WAFER
App. No. 11/707,408
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MEMORY WITH RESISTANCE MEMORY CELL AND EVALUATION CIRCUIT
App. No. 11/672,343
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METHOD AND SYSTEM FOR AN EXTENSIBLE CACHING FRAMEWORK
App. No. 11/701,193
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CLOCK RECEIVER CIRCUIT DEVICE, IN PARTICULAR FOR SEMI-CONDUCTOR COMPONENTS
App. No. 10/574,236
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CONTINUOUS SELF-CALIBRATION OF INTERNAL ANALOG SIGNALS
App. No. 11/649,047
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STORAGE MEDIUM HAVING A MANAGEABLE FILE DIRECTORY STRUCTURE
App. No. 11/641,496
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SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING A SEMICONDUCTOR MEMORY DEVICE
App. No. 10/569,859
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MRAM MEMORY CELL HAVING A WEAK INTRINSIC ANISOTROPIC STORAGE LAYER AND METHOD OF PRODUCING THE SAME
App. No. 11/634,988
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Method for the treatment of material, in particular in the fabrication of semiconductor components
App. No. 11/605,730
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MEMORY CELL ARRAY
App. No. 11/562,315
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METHOD FOR CONTINUOUS, FRAME-SPECIFIC CLICK-STREAM RECORDING
App. No. 11/601,357
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METHOD FOR OPERATING AN ELECTRICAL WRITABLE AND ERASABLE MEMORY CELL AND A MEMORY DEVICE FOR ELECTRICAL MEMORIES
App. No. 11/600,425
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METHOD FOR DETERMINING A RADIATION POWER AND AN EXPOSURE APPARATUS
App. No. 10/599,428
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ENERGY ADJUSTED WRITE PULSES IN PHASE-CHANGE MEMORIES
App. No. 11/524,131
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METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR SUBSTRATE COMPRISING A PLURALITY OF GATE STACKS ON A SEMICONDUCTOR SUBSTRATE, AND CORRESPONDING SEMICONDUCTOR STRUCTURE
App. No. 11/513,447
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CLOCK STOP DETECTOR
App. No. 11/504,923
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Phase change memory cell defined by a pattern shrink material process
App. No. 11/502,078
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METHOD FOR DETERMINING AN OPTIMAL ABSORBER STACK GEOMETRY OF A LITHOGRAPHIC REFLECTION MASK
App. No. 11/500,383
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METHOD FOR APPLYING REWIRING TO A PANEL WHILE COMPENSATING FOR POSITION ERRORS OF SEMICONDUCTOR CHIPS IN COMPONENT POSITIONS OF THE PANEL
App. No. 10/566,454
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PROGRAMMABLE RESISTIVE MEMORY CELL WITH A PROGRAMMABLE RESISTANCE LAYER
App. No. 11/452,417
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A SYSTEM USING CONTENT GENERATOR FOR DYNAMICALLY REGENERATING ONE OR MORE FRAGMENTS OF WEB PAGE BASED ON NOTIFICATION OF CONTENT CHANGE
App. No. 11/444,020
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System and method for the dynamic provisioning of static content
App. No. 11/444,023
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DUTY CYCLE CORRECTOR
App. No. 11/442,842
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INTEGRATED CIRCUIT HAVING A RESISTIVE MEMORY
App. No. 11/441,805
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SIMULATING A FLOATING WORDLINE CONDITION IN A MEMORY DEVICE, AND RELATED TECHNIQUES
App. No. 11/437,669
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INTEGRATED SEMICONDUCTOR MEMORY
App. No. 11/414,554
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INTEGRATED CIRCUIT, TEST SYSTEM AND METHOD FOR READING OUT AN ERROR DATUM FROM THE INTEGRATED CIRCUIT
App. No. 11/415,443
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MAGNETORESISTIVE MEMORY CELL AND PROCESS FOR PRODUCING THE SAME
App. No. 11/412,067
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STANDBY CURRENT REDUCTION OVER A PROCESS WINDOW WITH A TRIMMABLE WELL BIAS
App. No. 11/402,412
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METHOD AND APPARATUS FOR MASKING KNOWN FAILS DURING MEMORY TESTS READOUTS
App. No. 11/397,790
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MEMORY ARRANGEMENT HAVING A PLURALITY OF RAM CHIPS
App. No. 11/394,142
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Delay locked loop device
App. No. 11/391,696
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SYNCHRONOUS RAM MEMORY CIRCUIT
App. No. 11/390,557
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INTEGRATED CIRCUIT WITH ELECTROSTATIC DISCHARGE PROTECTION
App. No. 11/389,540
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SYSTEM AND METHOD FOR TESTING ONE OR MORE DIES ON A SEMICONDUCTOR WAFER
App. No. 11/386,512
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CLOCK SIGNAL INPUT/OUTPUT DEVICE FOR CORRECTING CLOCK SIGNALS
App. No. 11/374,990
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METHOD OF MODELING PRODUCT DEMAND SUBJECT TO A LARGE NUMBER OF INTERACTIONS
App. No. 11/373,747
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DEVICE AND METHOD FOR TESTING AN ELECTRIC CIRCUIT
App. No. 11/372,754
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METHOD FOR PRODUCING SEMICONDUCTOR MEMORY DEVICES AND INTEGRATED MEMORY DEVICE
App. No. 11/371,743
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SELF-ALIGNED V0-CONTACT FOR CELL SIZE REDUCTION
App. No. 11/373,080
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MULTICHIP PACKAGE WITH CLOCK FREQUENCY ADJUSTMENT
App. No. 11/370,559
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SEMICONDUCTOR MODULE FOR MAKING ELECTRICAL CONTACT WITH A CONNECTION DEVICE VIA A REWIRING DEVICE
App. No. 11/364,770
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INTEGRATED CIRCUIT COMPRISING AN ORGANIC SEMICONDUCTOR, AND METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT
App. No. 11/362,960
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METHOD AND SYSTEM FOR FACILITATING MARKETING DIALOGUES
App. No. 11/353,792
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