Integrated circuit including a gate electrode
View Patent ↗An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.
1. An integrated circuit, comprising:
a transistor, comprising a first source/drain electrode;
a second source/drain electrode;
a channel arranged in a longitudinal direction between the first and the second source/drain electrode in a semiconductor substrate, the channel disposed vertically within the semiconductor substrate in a direction from an upper surface to a rear surface of the semiconductor substrate;
a gate electrode, which is arranged adjacent the channel layer and is electrically insulated from the channel layer; and
a semiconductor substrate electrode arranged on a rear side of the semiconductor substrate, wherein
the gate electrode is disposed vertically within the semiconductor substrate and includes a first gate electrode disposed on a first lateral side of the channel and a second gate electrode disposed on a second lateral side of the channel such that the gate electrode encloses the channel on least the two opposite lateral sides.
2. The integrated circuit of claim 1 , wherein the gate electrode includes a horizontal portion disposed on a top side of the channel between the channel and the upper surface of the semiconductor substrate such that the gate electrode is formed approximately in U-shaped fashion in cross section and encloses the channel at three sides.
3. The integrated circuit of claim 1 , wherein the top side of the channel is adjacent to and space from the horizontal upper surface of the semiconductor substrate.
4. The integrated circuit of claim 1 , wherein the channel is formed essentially as a web on the semiconductor substrate.
5. The integrated circuit of claim 1 , wherein the channel has an essentially homogeneous doping over the channel height.
6. The integrated circuit of claim 1 , wherein the channel doping has a doping atom concentration of at most 1*10 17 cm −3 and a doping atom concentration of at least 5*10 17 cm −3 is present below the channel.
7. The integrated circuit of claim 6 , wherein the channel length in the longitudinal direction corresponds at least to 2.5 times the channel width in the lateral direction.
8. The integrated circuit of claim 1 , wherein the channel doping decreases over the channel length toward the source/drain electrode connected to a capacitor electrode, the doping atom concentration at the source/drain electrode connected to the capacitor electrode being at most 5*10 17 cm −3 .
9. The integrated circuit of claim 8 , wherein the channel length in the longitudinal direction corresponds at least to the channel width in the lateral direction.
10. The integrated circuit of claim 1 , wherein a top side of the channel extends along and is spaced from a planar surface of the semiconductor substrate.
11. The integrated circuit of claim 1 , wherein a top side of the channel is spaced from and extends approximately horizontally with respect to the semiconductor substrate.