Patent Assignment
Reel/Frame 036873/0758
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-10-15
Received: 2015-10-15
Pages: 13
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IEX, IRELAND
Covered Applications
(100)
INTEGRATED CIRCUIT COMPRISING AN ORGANIC SEMICONDUCTOR, AND METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT
App. No. 12/188,966
→
INTEGRATED CIRCUIT INCLUDING A GATE ELECTRODE
App. No. 11/926,653
→
METHOD AND APPARATUS FOR MASKING KNOWN FAILS DURING MEMORY TESTS READOUTS
App. No. 11/397,790
→
INTEGRATED CIRCUIT COMPRISING AN ORGANIC SEMICONDUCTOR, AND METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT
App. No. 11/362,960
→
Semiconductor memory having a short effective word line cycle time and method for reading data from a semiconductor memory of this type
App. No. 11/333,758
→
INTEGRATED CIRCUIT
App. No. 11/329,363
→
SOLUTION AND METHOD FOR THE TREATMENT OF A SUBSTRATE, AND SEMICONDUCTOR COMPONENT
App. No. 11/318,065
→
INTEGRATED SEMICONDUCTOR STORAGE WITH AT LEAST A STORAGE CELL AND PROCEDURE
App. No. 11/283,804
→
SELECTIVE BANK REFRESH
App. No. 11/249,773
→
INTEGRATED SEMICONDUCTOR CIRCUIT COMPRISING A TRANSISTOR AND A STRIP CONDUCTOR
App. No. 11/213,342
→
INTEGRATED ELECTRONIC COMPONENT
App. No. 11/211,168
→
SEMICONDUCTOR MEMORY HAVING CHARGE TRAPPING MEMORY CELLS AND FABRICATION METHOD
App. No. 11/145,541
→
MEMORY SYSTEM FOR NETWORK BROADCASTING APPLICATIONS AND METHOD FOR OPERATING THE SAME
App. No. 11/132,419
→
NON-VOLATILE MEMORY CELL, MEMORY CELL ARRANGEMENT AND METHOD FOR PRODUCTION OF A NON-VOLATILE MEMORY CELL
App. No. 10/533,215
→
METHOD FOR PRODUCTION OF A SEMICONDUCTOR STRUCTURE
App. No. 11/065,342
→
METHOD AND DEVICE FOR VARYING AN ACTIVE DUTY CYCLE OF A WORDLINE
App. No. 11/048,836
→
MULTILAYER CIRCUIT CARRIER, PANEL, ELECTRONIC DEVICE, AND METHOD FOR PRODUCING A MULTILAYER CIRCUIT CARRIER
App. No. 11/046,892
→
CIRCUIT ARRANGEMENT AND METHOD FOR DRIVING ELECTRONIC CHIPS
App. No. 10/853,768
→
METHOD FOR REDUCING AN OVERLAY ERROR AND MEASUREMENT MARK FOR CARRYING OUT THE SAME
App. No. 10/952,885
→
SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING A SEMICONDUCTOR MEMORY
App. No. 10/911,230
→
METHOD FOR THE LATERAL CONTACTING OF A SEMICONDUCTOR CHIP
App. No. 10/901,931
→
CALIBRATION DEVICE FOR THE CALIBRATION OF A TESTER CHANNEL OF A TESTER DEVICE AND A TEST SYSTEM
App. No. 10/894,942
→
CIRCUIT AND METHOD FOR CONTROLLING AN ACCESS TO AN INTEGRATED MEMORY
App. No. 10/892,251
→
INTEGRATED SEMICONDUCTOR CIRCUIT WITH AN ELECTRICALLY PROGRAMMABLE SWITCHING ELEMENT
App. No. 10/886,017
→
INTEGRATED CLOCK SUPPLY CHIP FOR A MEMORY MODULE, MEMORY MODULE COMPRISING THE INTEGRATED CLOCK SUPPLY CHIP, AND METHOD FOR OPERATING THE MEMORY MODULE UNDER TEST CONDITIONS
App. No. 10/886,523
→
ARRANGEMENT FOR FEEDING OR DISSIPATING HEAT TO/FROM A SEMICONDUCTOR SUBSTRATE FOR THE PURPOSE OF PREPARING OR POST-PROCESSING A LITHOGRAPHIC PROJECTION STEP
App. No. 10/883,623
→
CIRCUIT AND METHOD FOR REFRESHING MEMORY CELLS OF A DYNAMIC MEMORY
App. No. 10/881,706
→
METHOD FOR CREATING ALTERNATING PHASE MASKS
App. No. 10/881,703
→
CIRCUIT AND METHOD FOR REFRESHING MEMORY CELLS OF A DYNAMIC MEMORY
App. No. 10/881,689
→
SEMICONDUCTOR MEMORY
App. No. 10/878,676
→
BURIED STRAP CONTACT FOR A STORAGE CAPACITOR AND METHOD FOR FABRICATING IT
App. No. 10/875,787
→
TEST SYSTEM FOR TESTING INTEGRATED CHIPS AND AN ADAPTER ELEMENT FOR A TEST SYSTEM
App. No. 10/865,050
→
SEMI-CONDUCTOR COMPONENT TESTING PROCESS AND SYSTEM FOR TESTING SEMI-CONDUCTOR COMPONENTS
App. No. 10/860,594
→
ERROR DETECTION IN A CIRCUIT MODULE
App. No. 10/857,596
→
SEMICONDUCTOR GATE STRUCTURE AND METHOD FOR FABRICATING A SEMICONDUCTOR GATE STRUCTURE
App. No. 10/854,772
→
MEMORY DEVICE FOR STORING ELECTRICAL CHARGE AND METHOD FOR FABRICATING THE SAME
App. No. 10/853,734
→
MASK SET HAVING SEPARATE MASKS TO FORM DIFFERENT REGIONS OF INTEGRATED CIRCUIT CHIPS, EXPOSURE SYSTEM INCLUDING THE MASK SET WITH AN APERTURE DEVICE, AND METHOD OF USING THE MASK SET TO EXPOSE A SEMICONDUCTOR WAFER
App. No. 10/852,661
→
INTEGRATED CIRCUIT, IN PARTICULAR INTEGRATED MEMORY, AND METHODS FOR OPERATING AN INTEGRATED CIRCUIT
App. No. 10/852,116
→
MEMORY ARRANGEMENT
App. No. 10/850,382
→
METHOD AND APPARATUS FOR OPTIMIZING THE FUNCTIONING OF DRAM MEMORY ELEMENTS
App. No. 10/850,817
→
METHOD AND ARRANGEMENT FOR TESTING OUTPUT CIRCUITS OF HIGH SPEED SEMICONDUCTOR MEMORY DEVICES
App. No. 10/843,383
→
GASSING-FREE EXPOSURE MASK
App. No. 10/843,669
→
CIRCUIT ARRANGEMENT AND METHOD FOR SETTING A VOLTAGE SUPPLY FOR A READ/WRITE AMPLIFIER OF AN INTEGRATED MEMORY
App. No. 10/841,546
→
INTEGRATED SEMICONDUCTOR STORAGE WITH AT LEAST A STORAGE CELL AND PROCEDURE
App. No. 10/840,328
→
CONNECTION BETWEEN A SEMICONDUCTOR CHIP AND AN EXTERNAL CONDUCTOR STRUCTURE AND METHOD FOR PRODUCING IT
App. No. 10/842,259
→
DRAM MEMORY CELL
App. No. 10/839,800
→
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE
App. No. 10/836,143
→
METHOD FOR DETERMINING THE DEPTH OF A BURIED STRUCTURE
App. No. 10/835,259
→
DEVICE AND METHOD FOR CORRECTING THE DUTY CYCLE OF A CLOCK SIGNAL
App. No. 10/834,385
→
LATCH OR PHASE DETECTOR DEVICE
App. No. 10/834,378
→
DEVICES FOR SYNCHRONIZING CLOCK SIGNALS
App. No. 10/834,383
→
FIELD-EFFECT TRANSISTOR
App. No. 10/830,675
→
METHOD FOR SETTING A TERMINATION VOLTAGE AND AN INPUT CIRCUIT
App. No. 10/831,623
→
INPUT RECEIVER CIRCUIT
App. No. 10/831,001
→
INTEGRATED MEMORY CIRCUIT HAVING A REDUNDANCY CIRCUIT AND A METHOD FOR REPLACING A MEMORY AREA
App. No. 10/831,466
→
DEVICE FOR COOLING MEMORY MODULES
App. No. 10/829,362
→
MEMORY MODULE HAVING SPACE-SAVING ARRANGEMENT OF MEMORY CHIPS AND MEMORY CHIP THEREFORE
App. No. 10/828,034
→
METHOD FOR IMPROVING THE MECHANICAL PROPERTIES OF BOC MODULE ARRANGEMENTS
App. No. 10/826,601
→
INTEGRATED DYNAMIC MEMORY HAVING A CONTROL CIRCUIT FOR CONTROLLING A REFRESH MODE FOR MEMORY CELLS
App. No. 10/823,608
→
MEMORY APPARATUS HAVING A SHORT WORD LINE CYCLE TIME AND METHOD FOR OPERATING A MEMORY APPARATUS
App. No. 10/822,997
→
METHOD AND APPARATUS FOR TESTING DRAM MEMORY CHIPS IN MULTICHIP MEMORY MODULES
App. No. 10/822,529
→
DRIVER CIRCUIT HAVING A PLURALITY OF DRIVERS FOR DRIVING SIGNALS IN PARALLEL
App. No. 10/819,222
→
REFRESHING DYNAMIC MEMORY CELLS IN A MEMORY CIRCUIT AND A MEMORY CIRCUIT
App. No. 10/817,469
→
METHOD AND APPARATUS FOR ORIENTING SEMICONDUCTOR WAFERS IN SEMICONDUCTOR FABRICATION
App. No. 10/816,184
→
DATA MEMORY CIRCUIT
App. No. 10/817,504
→
INTEGRATED MEMORY HAVING A VOLTAGE GENERATOR CIRCUIT FOR GENERATING A VOLTAGE SUPPLY FOR A READ/WRITE AMPLIFIER
App. No. 10/815,856
→
INPUT CIRCUIT FOR RECEIVING A SIGNAL AT AN INPUT ON AN INTEGRATED CIRCUIT
App. No. 10/815,541
→
METHOD FOR FABRICATING TRANSISTORS OF DIFFERENT CONDUCTION TYPES AND HAVING DIFFERENT PACKING DENSITIES IN A SEMICONDUCTOR SUBSTRATE
App. No. 10/812,876
→
SEMICONDUCTOR DEVICE VOLTAGE SUPPLY FOR A SYSTEM WITH AT LEAST TWO, ESPECIALLY STACKED, SEMICONDUCTOR DEVICES
App. No. 10/812,395
→
METHOD FOR FABRICATING A CONTACT HOLE PLANE IN A MEMORY MODULE
App. No. 10/811,509
→
INTEGRATED CIRCUIT WITH A TEST CIRCUIT
App. No. 10/810,489
→
ARRANGEMENT FOR TRANSFERRING INFORMATION/STRUCTURES TO WAFERS
App. No. 10/802,618
→
PROCESS FOR PRODUCING AN ETCHING MASK ON A MICROSTRUCTURE, IN PARTICULAR A SEMICONDUCTOR STRUCTURE WITH TRENCH CAPACITORS, AND CORRESPONDING USE OF THE ETCHING MASK
App. No. 10/801,781
→
INSULATOR STRUCTURE AND METHOD FOR PRODUCING INSULATOR STRUCTURES IN A SEMICONDUCTOR SUBSTRATE
App. No. 10/798,863
→
INTEGRATED MEMORY HAVING REDUNDANT UNITS OF MEMORY CELLS AND METHOD FOR TESTING AN INTEGRATED MEMORY
App. No. 10/798,334
→
METHOD AND TEST CIRCUIT FOR TESTING A DYNAMIC MEMORY CIRCUIT
App. No. 10/798,245
→
SET OF MASKS INCLUDING A FIRST MASK AND A SECOND TRIMMING MASK WITH A SEMITRANSPARENT REGION HAVING A TRANSPARENCY BETWEEN 20% AND 80% TO CONTROL DIFFRACTION EFFECTS AND OBTAIN MAXIMUM DEPTH OF FOCUS FOR THE PROJECTION OF STRUCTURE PATTERNS ONTO A SEMICONDUCTOR WAF
App. No. 10/792,693
→
TEST APPARATUS FOR TESTING INTEGRATED MODULES AND METHOD FOR OPERATING A TEST APPARATUS
App. No. 10/791,768
→
SET OF AT LEAST TWO MASKS FOR THE PROJECTION OF STRUCTURE PATTERNS
App. No. 10/791,763
→
BUFFER CHIP AND METHOD FOR CONTROLLING ONE OR MORE MEMORY ARRANGEMENTS
App. No. 10/792,408
→
METHOD FOR FORMING AN OPENING IN A LIGHT-ABSORBING LAYER ON A MASK
App. No. 10/789,994
→
CAPACITOR ARRANGEMENT WITH CAPACITORS ARRANGED ONE IN THE OTHER
App. No. 10/787,934
→
INTEGRATED SEMICONDUCTOR CIRCUIT HAVING A CELL ARRAY HAVING A MULTIPLICITY OF MEMORY CELLS
App. No. 10/787,119
→
INTEGRATED SEMICONDUCTOR CIRCUIT HAVING A MULTIPLICITY OF MEMORY CELLS
App. No. 10/785,087
→
CIRCUIT MODULE HAVING INTERLEAVED GROUPS OF CIRCUIT CHIPS
App. No. 10/785,140
→
METHOD AND TEST DEVICE FOR DETERMINING A REPAIR SOLUTION FOR A MEMORY MODULE
App. No. 10/784,134
→
DEVICE AND METHOD FOR CONVERTING AN INPUT SIGNAL
App. No. 10/783,068
→
INTEGRATED MODULE HAVING A DELAY ELEMENT
App. No. 10/783,377
→
DLL CIRCUIT FOR STABILIZATION OF THE INITIAL TRANSIENT PHASE
App. No. 10/780,284
→
INTEGRATED TEST CIRCUIT IN AN INTEGRATED CIRCUIT
App. No. 10/780,104
→
ARCHITECTURE FOR VERTICAL TRANSISTOR CELLS AND TRANSISTOR-CONTROLLED MEMORY CELLS
App. No. 10/777,128
→
METHOD AND CIRCUIT FOR ALLOCATING MEMORY ARRANGEMENT ADDRESSES
App. No. 10/777,992
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MEMORY MODULE HAVING A PLURALITY OF INTEGRATED MEMORY COMPONENTS
App. No. 10/776,467
→
MEMORY MODULE HAVING A PLURALITY OF INTEGRATED MEMORY COMPONENTS
App. No. 10/776,178
→
METHOD FOR EXPOSING A SUBSTRATE WITH A STRUCTURE PATTERN WHICH COMPENSATES FOR THE OPTICAL PROXIMITY EFFECT
App. No. 10/771,302
→
PROCESS FOR PRODUCING ALUMINUM-FILLED CONTACT HOLES
App. No. 10/768,241
→
SECURITY MEMORY CARD AND PRODUCTION METHOD
App. No. 10/769,286
→
FINFET DEVICE AND METHOD OF FABRICATION
App. No. 10/765,910
→
METHOD OF FABRICATING AN OXIDE COLLAR FOR A TRENCH CAPACITOR
App. No. 10/765,052
→
RAM STORE AND CONTROL METHOD THEREFOR
App. No. 10/762,280
→