Integrated semiconductor storage with at least a storage cell and procedure
View Patent ↗The invention relates to an integrated semiconductor memory with at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region and a region arranged between the first and the second source/drain region, the structure element is insulated from a semiconductor substrate by an insulation layer, a gate dielectric being arranged on the structure element and a word line being arranged on the gate dielectric.
1. A method for fabricating an integrated semiconductor memory with at least one memory cell including a transistor and a storage capacitor, said method comprising the steps of:
a) providing a semiconductor substrate including an insulation layer and a layer made of semiconductor material on the insulation layer,
b) patterning the layer made of semiconductor material to form structure elements separated from one another,
c) forming a gate dielectric on the surface of a structure element,
d) depositing at least one gate layer,
e) forming a word line by patterning the at least one gate layer, and
f) completing a transistor by implanting a first and a second source/drain region into the structure element at opposed ends of the structure element.
2. The method as claimed in claim 1 , wherein in step c) further comprises, forming a second region of the gate dielectric wherein, said second region including a layer thickness greater than the layer thickness of the first region of the gate dielectric.
3. The method as claimed in claim 2 , wherein prior to forming the gate dielectric, a nitrogen dopant is introduced into a partial region of the structure element.
4. The method as claimed in claim 1 , wherein the nitrogen dopant is introduced into a partial region of the structure element which is arranged directly below a top side of the structure element, said top side being opposed to the insulation layer, whereas a region of the structure element which is arranged nearer to the insulation layer is free of a nitrogen dopant.
5. The method as claimed in claim 1 , wherein step c) further comprises: forming at least one first region of the gate dielectric, and the formation of the first region of the gate dielectric being terminated at approximately a point in time at which the first region of the gate dielectric has a layer thickness which is so small that, in the switched-off state of the transistor, majority charge carriers generated thermally in the structure element pass into the word line by direct tunneling through the gate dielectric.