DRAM memory cell
View Patent ↗A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.
1. A DRAM memory cell, comprising:
a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode;
a second source/drain electrode;
a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate;
a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer;
a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor; and
a semiconductor substrate electrode on a rear side, wherein
the gate electrode encloses the channel layer at at least two opposite sides.
2. A DRAM memory cell, comprising:
a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode;
a second source/drain electrode;
a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate;
a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer;
a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor; and
a semiconductor substrate electrode on a rear side, wherein
the gate electrode encloses the channel layer at at least two opposite sides,
wherein the gate electrode is formed essentially in U-shaped fashion in cross section and encloses the channel layer at three sides.
3. The DRAM memory cell as claimed in claim 1 , wherein a word line that is electrically conductively connected to the gate electrode runs transversely over the channel layer.
4. The DRAM memory cell as claimed in claim 1 , wherein the channel layer is formed essentially in web-type fashion on the semiconductor substrate.
5. The DRAM memory cell as claimed in claim 1 , wherein the channel layer has an essentially homogeneous doping over the channel layer height.
6. The DRAM memory cell as claimed in claim 1 , wherein the channel layer doping has a doping atom concentration of at most 1*10 17 cm −3 and a doping atom concentration of at least 5*10 17 cm −3 is present below the channel layer.
7. The DRAM memory cell as claimed in claim 6 , wherein the channel layer length corresponds at least to 2.5 times the channel layer width.
8. The DRAM memory cell as claimed in claim 1 , wherein the channel layer doping decreases over the channel layer length toward the source/drain electrode connected to the capacitor electrode, the doping atom concentration at the source/drain electrode connected to the capacitor electrode being at most 5*10 17 cm −3 .
9. The DRAM memory cell as claimed in claim 8 , wherein the channel layer length corresponds at least to the channel layer width.
10. The DRAM memory cell as claimed in claim 1 , wherein the storage capacitor is formed as a trench capacitor arranged in a manner laterally adjoining the selection transistor, an inner capacitor electrode arranged in a trench being electrically conductively connected to one source/drain electrode.
11. The DRAM memory cell as claimed in claim 10 , wherein one source/drain electrode is arranged over an inner capacitor electrode arranged in the trench.
12. The DRAM memory cell as claimed in claim 1 , wherein the storage capacitor is formed as a stacked capacitor arranged in a manner laterally adjoining the selection transistor, an inner capacitor electrode being electrically conductively connected to one source/drain electrode.
13. A DRAM memory having a plurality of DRAM memory cells, the DRAM memory cells are arranged in matrix-type fashion on a semiconductor substrate and comprise:
a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode;
a second source/drain electrode;
a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate;
a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer;
a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor; and
a semiconductor substrate electrode on a rear side, wherein
the gate electrode encloses the channel layer at at least two opposite sides.