Integrated semiconductor storage with at least a storage cell and procedure

1. An integrated semiconductor memory with at least one memory cell including at least one transistor which forms an inversion channel in the switched-on state, the transistor comprising:

a structure element further containing a semiconductor material, the structure element comprising a first source/drain region, a second source/drain region and a region disposed between the first and the second source/drain region, the structure element being insulated from a semiconductor substrate by an insulation layer; and a gate dielectric disposed on the structure element and a word line disposed on the gate dielectric, the gate dielectric comprising a high-resistance tunnel contact including a first region, the layer thickness of which is such that, in the switched-off state of the transistor, majority charge carriers generated thermally in the structure element pass into the word line by direct tunneling through the gate dielectric, and the entire region of the structure element which region is disposed between the first and the second source/drain region being depleted of majority charge carriers in the switched-on state of the transistor.

2. The semiconductor memory as claimed in claim 1 , wherein a plurality of memory cells are connected to the word line.

3. The semiconductor memory as claimed in claim 2 , wherein the memory cell is a dynamic memory cell and the transistor comprises a selection transistor, and the memory cell has a storage capacitor, which is electrically coupled to the first source/drain region.

4. The semiconductor memory as claimed in claim 3 , wherein the storage capacitor is comprises a trench capacitor including an inner capacitor electrode, an outer capacitor electrode and a capacitor dielectric, and, on the bottom side of the insulation layer, the distance between the inner capacitor electrode and the outer capacitor electrode is of exactly the same magnitude as at a bottom of the trench capacitor.

5. The semiconductor memory as claimed in claim 4 , wherein the inner capacitor electrode extends to the bottom side of the insulation layer and is coupled by a contact to the first source/drain region of the selection transistor.

6. The semiconductor memory as claimed in claim 5 , wherein a top side of the contact, said top side being disposed on the same side of the insulation layer as the structure element, is arranged nearer to the insulation layer than the top side of the structure element, and the contact is insulated from a further word line by an insulating upper filling structure.

7. The semiconductor memory as claimed in claim 1 , wherein the structure element is disposed on an insulation layer, the first source/drain region is arranged in the structure element at one lateral end of the structure element and the second source/drain region is arranged in the structure element at another lateral end in the structure element, and between the two ends of the structure element, a top side of the structure element, said top side being opposed to the insulation layer, and side faces of the structure element which adjoin the top side are covered with an arrangement of layers comprising a gate dielectric and a gate electrode.

8. The semiconductor memory as claimed in claim 7 , wherein the arrangement of layers having the gate dielectric and the gate electrode covers the top side of the structure element, said top side being opposed to the insulation layer, and the side faces of the structure element which adjoin the top side.

9. The semiconductor memory as claimed in claim 1 , wherein the gate dielectric has a second region, which has a layer thickness greater than the layer thickness of the first region.

10. The semiconductor memory as claimed in claim 9 , wherein the first region of the gate dielectric is arranged on the top side of the structure element, said top side being opposed to the insulation layer, and the second region comprises the side faces of the structure element.

11. The semiconductor memory as claimed in claim 1 , wherein a nitrogen dopant is introduced into the structure element adjoining the first region of the gate dielectric.

12. The semiconductor memory as claimed in claim 1 , wherein the gate dielectric has a layer thickness of less than approximately 3 nm.

13. The semiconductor memory as claimed in claim 1 , wherein the semiconductor substrate is doped below the insulation layer.

14. The semiconductor memory as claimed in claim 1 , wherein a bit line contact is in contact with an end face of the structure element.

15. The semiconductor memory as claimed in claim 1 , wherein a spacer is arranged beside the word line, said spacer having an outer surface arranged flush with a lateral end of the structure element.

16. The semiconductor memory as claimed in claim 1 , wherein a bit line is arranged above the structure element, wherein the bit line runs in the direction of main extension of the structure element and is connected to the second source/drain region.

17. The semiconductor memory as claimed in claim 1 , wherein the semiconductor memory has a multiplicity of memory cells comprising transistors, a bit line contact being arranged at approximately every second crossover between a bit line and a word line and a word line passing above or below a storage capacitor at the remaining crossovers.

18. The semiconductor memory as claimed in claim 1 , wherein the structure element is formed in parallelepipedal fashion.

19. The semiconductor memory as claimed in claim 1 , wherein the gate dielectric has layer thickness between approximately 2 and 3 nm. in the first region.