Patent Assignment
Reel/Frame 023796/0001
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2010-01-15
Received: 2010-01-15
Pages: 393
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2006-04-25
Assignee
QIMONDA AG
GUSTAV-HEINEMANN-RING 212, MUNICH, DEX, 81739, GERMANY
Covered Applications
(100)
APPARATUS AND METHOD FOR MONITORING TRENCH PROFILES AND FOR SPECTROMETROLOGIC ANALYSIS
App. No. 11/407,339
→
SECURE MEDIA PATH METHODS, SYSTEMS, AND ARCHITECTURES
App. No. 11/275,990
→
METHOD FOR CONTROLLING A THICKNESS OF A FIRST LAYER AND METHOD FOR ADJUSTING THE THICKNESS OF DIFFERENT FIRST LAYERS
App. No. 11/295,726
→
SEMICONDUCTOR MEMORY DEVICE
App. No. 11/205,402
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SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
App. No. 11/177,281
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DUAL FREQUENCY FIRST-IN-FIRST-OUT STRUCTURE
App. No. 11/168,818
→
WIRELESS ECG SYSTEM
App. No. 11/077,934
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ORGANIC DIELECTRIC ELECTRONIC INTERCONNECT STRUCTURES AND METHOD FOR MAKING
App. No. 11/074,848
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SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER
App. No. 11/059,569
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PERFORMANCE TEST BOARD
App. No. 11/000,252
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PROCESS FOR REMOVING A RESIDUE FROM A METAL STRUCTURE ON A SEMICONDUCTOR SUBSTRATE
App. No. 10/995,025
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SEMICONDUCTOR DEVICE
App. No. 10/986,060
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FERROELECTRIC MEMORY DEVICE
App. No. 10/963,589
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METHOD OF ETCHING SILICON ANISOTROPICALLY
App. No. 10/943,017
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SEMICONDUCTOR MEMORY
App. No. 10/931,978
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GATE CONDUCTOR ISOLATION AND METHOD FOR MANUFACTURING SAME
App. No. 10/912,005
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METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
App. No. 10/886,668
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METHOD FOR PROVIDING WHISKER-FREE ALUMINUM METAL LINES OR ALUMINUM ALLOY LINES IN INTEGRATED CIRCUITS
App. No. 10/868,309
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SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
App. No. 10/849,111
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INTEGRATED SEMICONDUCTOR STORAGE WITH AT LEAST A STORAGE CELL AND PROCEDURE
App. No. 10/840,328
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CONNECTION BETWEEN A SEMICONDUCTOR CHIP AND AN EXTERNAL CONDUCTOR STRUCTURE AND METHOD FOR PRODUCING IT
App. No. 10/842,259
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METHOD FOR IMPROVING THE MECHANICAL PROPERTIES OF BOC MODULE ARRANGEMENTS
App. No. 10/826,601
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METHOD TO REDUCE NUMBER OF WIRE-BOND LOOP HEIGHTS VERSUS THE TOTAL QUANTITY OF POWER AND SIGNAL RINGS
App. No. 10/801,764
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METHOD FOR FORMING A TOP OXIDE WITH NITRIDE LINER
App. No. 10/798,865
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INTEGRATED TEST CIRCUIT IN AN INTEGRATED CIRCUIT
App. No. 10/780,104
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METHOD FOR EXPOSING A SUBSTRATE WITH A STRUCTURE PATTERN WHICH COMPENSATES FOR THE OPTICAL PROXIMITY EFFECT
App. No. 10/771,302
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METHOD AND PACKAGING STRUCTURE FOR OPTIMIZING WARPAGE OF FLIP CHIP ORGANIC PACKAGES
App. No. 10/771,728
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TEST STRUCTURE FOR IMPROVED VERTICAL MEMORY ARRAYS
App. No. 10/766,902
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RAM STORE AND CONTROL METHOD THEREFOR
App. No. 10/762,280
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A SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR USING A FERROELECTRIC MATERIAL
App. No. 10/760,499
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BUFFER AMPLIFIER ARCHITECTURE FOR SEMICONDUCTOR MEMORY CIRCUITS
App. No. 10/759,103
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DEVICE ARCHITECTURE AND PROCESS FOR IMPROVED VERTICAL MEMORY ARRAYS
App. No. 10/748,332
→
METHOD FOR FORMING A STRUCTURE ELEMENT ON A WAFER BY MEANS OF A MASK AND A TRIMMING MASK ASSIGNED HERETO
App. No. 10/743,105
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INTEGRATED SEMICONDUCTOR MEMORY CIRCUIT AND A METHOD FOR OPERATING THE SAME
App. No. 10/742,761
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MEMORY MODULE WITH A TEST DEVICE
App. No. 10/737,776
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METHOD FOR PRODUCTION OF CONTACTS ON A WAFER
App. No. 10/739,477
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METHOD FOR INSPECTION OF PERIODIC GRATING STRUCTURES ON LITHOGRAPHY MASKS
App. No. 10/735,414
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INTEGRATED DRAM SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING THE SAME
App. No. 10/733,332
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ARRANGEMENT FOR THE PROTECTION OF THREE-DIMENSIONAL STRUCTURES ON WAFERS
App. No. 10/732,979
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SEMICONDUCTOR MEMORY HAVING AN ARRANGEMENT OF MEMORY CELLS
App. No. 10/731,109
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INTEGRATED SEMICONDUCTOR MEMORY WITH A SELECTION TRANSISTOR FORMED AT A RIDGE
App. No. 10/727,595
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METHOD OF FORMING FILLED BLIND VIAS
App. No. 10/729,174
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DYNAMIC RAM SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING THE MEMORY
App. No. 10/724,906
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CAPACITOR WITH ELECTRODES MADE OF RUTHENIUM AND METHOD FOR PATTERNING LAYERS MADE OF RUTHENIUM OR RUTHENIUM(IV) OXIDE
App. No. 10/724,134
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MEMORY MODULE AND METHOD FOR OPERATING A MEMORY MODULE IN A DATA MEMORY SYSTEM
App. No. 10/724,135
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REFLECTION MASK FOR PROJECTING A STRUCTURE ONTO A SEMICONDUCTOR WAFER AND METHOD FOR PRODUCING THE MASK
App. No. 10/723,631
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CIRCUIT AND METHOD FOR DETERMINING AT LEAST ONE VOLTAGE, CURRENT AND/OR POWER VALUE FOR AN INTEGRATED CIRCUIT
App. No. 10/723,905
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METHOD FOR PRODUCING AN INTEGRATED CIRCUIT WITH A REWIRING DEVICE AND CORRESPONDING INTEGRATED CIRCUIT
App. No. 10/721,745
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DYNAMIC MEMORY CELL
App. No. 10/723,289
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NOISY CLOCK TEST METHOD AND APPARATUS
App. No. 10/720,437
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TRANSISTOR ARRAY AND SEMICONDUCTOR MEMORY CONFIGURATION FABRICATED WITH THE TRANSISTOR ARRAY
App. No. 10/718,310
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METHOD FOR ADJUSTING A SUBSTRATE IN AN APPLIANCE FOR CARRYING OUT EXPOSURE
App. No. 10/717,413
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MEMORY SYSTEM AND MEMORY SUBSYSTEM
App. No. 10/715,145
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MEMORY CELL ARRAY
App. No. 10/713,689
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SEMICONDUCTOR DEVICE HAVING FERROELECTRIC FILM AND MANUFACTURING METHOD THEREOF
App. No. 10/706,970
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POLYMER TRANSISTOR ARRANGEMENT, INTEGRATED CIRCUIT ARRANGEMENT AND METHOD FOR PRODUCING A POLYMER TRANSISTOR ARRANGEMENT
App. No. 10/714,536
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METHOD FOR REPAIRING A PHOTOLITHOGRAPHIC MASK, AND A PHOTOLITHOGRAPHIC MASK
App. No. 10/703,298
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METHOD FOR MANUFACTURING A STACK ARRANGEMENT OF A MEMORY MODULE
App. No. 10/701,742
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STACK ARRANGEMENT OF A MEMORY MODULE
App. No. 10/700,871
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D-TYPE FLIP-FLOP WITH A REDUCED NUMBER OF TRANSISTORS
App. No. 10/699,135
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METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE
App. No. 10/696,159
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D-TYPE FLIPFLOP
App. No. 10/695,624
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METHOD FOR MINIMIZING THE VAPOR DEPOSITION OF TUNGSTEN OXIDE DURING THE SELECTIVE SIDE WALL OXIDATION OF TUNGSTEN-SILICON GATES
App. No. 10/694,593
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METHOD FOR PRODUCING VERTICAL PATTERNED LAYERS MADE OF SILICON DIOXIDE
App. No. 10/690,002
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SEMICONDUCTOR MODULE AND METHODS FOR FUNCTIONALLY TESTING AND CONFIGURING A SEMICONDUCTOR MODULE
App. No. 10/689,419
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METHOD FOR ALIGNING AND EXPOSING A SEMICONDUCTOR WAFER
App. No. 10/686,848
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CIRCUIT CONFIGURATION AND METHOD FOR MEASURING AT LEAST ONE OPERATING PARAMETER FOR AN INTEGRATED CIRCUIT
App. No. 10/681,498
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INTEGRATED MEMORY
App. No. 10/681,503
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METHOD AND APPARATUS FOR INTERNALLY TRIMMING OUTPUT DRIVERS AND TERMINATIONS IN SEMICONDUCTOR DEVICES
App. No. 10/680,782
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TEST SYSTEM AND METHOD FOR TESTING MEMORY CIRCUITS
App. No. 10/676,588
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MEMORY CIRCUIT AND METHOD FOR READING OUT DATA
App. No. 10/676,596
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TEST STRUCTURE FOR DETERMINING A REGION OF A DEEP TRENCH OUTDIFFUSION IN A MEMORY CELL ARRAY
App. No. 10/675,493
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METHOD AND FURNACE FOR THE VAPOR PHASE DEPOSITION OF COMPONENTS ONTO SEMICONDUCTOR SUBSTRATES WITH A VARIABLE MAIN FLOW DIRECTION OF THE PROCESS GAS
App. No. 10/675,049
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METHOD FOR COMMUNICATING A MEASURING POSITION OF A STRUCTURAL ELEMENT THAT IS TO BE FORMED ON A MASK
App. No. 10/675,772
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INTEGRATED SEMICONDUCTOR CIRCUIT CONFIGURATION
App. No. 10/675,761
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METHOD FOR CALIBRATING SEMICONDUCTOR DEVICES USING A COMMON CALIBRATION REFERENCE AND A CALIBRATION CIRCUIT
App. No. 10/675,492
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TEST STRUCTURE FOR DETERMINING A DOPING REGION OF AN ELECTRODE CONNECTION BETWEEN A TRENCH CAPACITOR AND A SELECTION TRANSISTOR IN A MEMORY CELL ARRAY
App. No. 10/675,051
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PSEUDOSTATIC MEMORY CIRCUIT
App. No. 10/675,433
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METHOD FOR THE PATTERNED, SELECTIVE METALLIZATION OF A SURFACE OF A SUBSTRATE
App. No. 10/675,634
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CALIBRATION CONFIGURATION
App. No. 10/673,965
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PHOTOSENSITIVE COATING MATERIAL FOR A SUBSTRATE AND PROCESS FOR EXPOSING THE COATED SUBSTRATE
App. No. 10/673,964
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METHOD FOR CONTROLLING SEMICONDUCTOR CHIPS AND CONTROL APPARATUS
App. No. 10/672,145
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INTEGRATED CIRCUIT HAVING AN INPUT CIRCUIT
App. No. 10/670,662
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DEFECT REPAIR METHOD, IN PARTICULAR FOR REPAIRING QUARTZ DEFECTS ON ALTERNATING PHASE SHIFT MASKS
App. No. 10/668,375
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PROCESS FOR DESIGNING AND MANUFACTURING SEMI-CONDUCTOR MEMORY COMPONENTS, IN PARTICULAR DRAM COMPONENTS
App. No. 10/668,684
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CIRCUIT DEVICE WITH CLOCK PULSE DETECTION FACILITY
App. No. 10/668,683
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PHOTOMASK, IN PARTICULAR ALTERNATING PHASE SHIFT MASK, WITH COMPENSATION STRUCTURE
App. No. 10/667,552
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ARRANGEMENT OF SEVERAL RESISTORS JOINTLY POSITIONED IN A WELL OF A SEMICONDUCTOR DEVICE, AND A SEMICONDUCTOR DEVICE INCLUDING AT LEAST ONE SUCH ARRANGEMENT
App. No. 10/663,354
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SEMICONDUCTOR DEVICE TESTING APPARATUS, SEMICONDUCTOR DEVICE TESTING SYSTEM, AND SEMICONDUCTOR DEVICE TESTING METHOD FOR MEASURING AND TRIMMING THE OUTPUT IMPEDANCE OF DRIVER DEVICES
App. No. 10/663,448
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TEST STRUCTURE FOR MEASURING A JUNCTION RESISTANCE IN A DRAM MEMORY CELL ARRAY
App. No. 10/659,843
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SEMI-CONDUCTOR COMPONENT WITH CLOCK RELAYING DEVICE
App. No. 10/658,741
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DIGITAL SIGNAL DELAY DEVICE
App. No. 10/658,742
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FABRICATION METHOD FOR A SEMICONDUCTOR STRUCTURE HAVING A PARTLY FILLED TRENCH
App. No. 10/660,091
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SYNCHRONIZATION DEVICE FOR A SEMICONDUCTOR MEMORY DEVICE
App. No. 10/659,693
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METHOD FOR DETERMINING THE END POINT FOR A CLEANING ETCHING PROCESS
App. No. 10/656,353
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METHOD FOR THE SOLDER-STOP STRUCTURING OF ELEVATIONS ON WAFERS
App. No. 10/656,042
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FENCE-FREE ETCHING OF IRIDIUM BARRIER HAVING A STEEP TAPER ANGLE
App. No. 10/654,376
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MASK FOR PROJECTING A STRUCTURE PATTERN ONTO A SEMICONDUCTOR SUBSTRATE
App. No. 10/653,537
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BARRRIER LAYER AND A METHOD FOR SUPPRESSING DIFFUSION PROCESSES DURING THE PRODUCTION OF SEMICONDUCTOR DEVICES
App. No. 10/653,599
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READ-OUT CIRCUIT FOR A DYNAMIC MEMORY CIRCUIT MEMORY CELL ARRAY AND METHOD FOR AMPLIFYING AND READING DATA STORED IN A MEMORY CELL ARRAY
App. No. 10/653,652
→