Memory system and memory subsystem

1. A memory system comprising:

a circuit board having a first means for receiving and a second means for receiving;

a first signal bus portion on said circuit board connected to said first means for receiving; and

a second signal bus portion on said circuit board connected to said second means for receiving and not connected to said first signal bus portion,

a first memory module received in said first means for receiving;

a second memory module received in said second means for receiving; and

a flexible bridge connecting said first and second memory modules for providing a signal bus between said memory modules, so that said first and second memory modules are serially connected between said first and second signal bus portions on said circuit board.

2. The memory system of claim 1 , wherein the memory modules are received in the respective means for receiving at a first side thereof and wherein the flexible bridge extends from a respective second side of the memory modules.

3. The memory system of claim 1 , wherein the respective second side of the memory module is arranged opposite to the first side thereof.

4. The memory system of claim 1 , wherein the receiving means are slot connectors for receiving memory modules adapted for DDR memory systems.

5. The memory system of claim 1 , wherein the flexible bridge comprises data lines and/or control signal lines for providing a data bus and/or a control signal bus between said memory modules.

6. The memory system of claim 1 , wherein a memory controller is provided on said circuit board and connected to said first signal bus portion, wherein said first signal bus portion provides a data bus and/or a control signal bus between said controller and said first memory module.

7. The memory system of claim 6 , wherein said first signal bus portion further provides a clock bus between said memory controller and said first memory modules.

8. The memory system of claim 1 , further comprising third means for receiving on said circuit board and wherein said second signal bus portion connects said second means for receiving to said third means for receiving.

9. The memory system of claim 1 , wherein the bridge is a flexible printed circuit board having a ground layer and a signal layer.

10. The memory system of claim 1 , wherein said signal bus provided by said flexible bridge has a trace impedance matched to a trace impedance of said bus portions on the circuit board and matched to a trace impedance of bus portions on said memory modules.

11. The memory system of claim 1 , wherein the circuit board comprises four means for receiving and wherein the flexible bridge has a length permitting the first and second means for receiving to be separated by two other means for receiving.

12. The memory system of claim 1 wherein said first and second receiving means are first and second slot connectors each for receiving a single memory module.

13. A memory system comprising:

a circuit board having a first slot connector for receiving a single memory module and a second slot connector for receiving a single memory module;

a first signal bus portion on said circuit board connected to said first slot connector;

a second signal bus portion on said circuit board having a first end connected to said second slot connector and not connected to said first signal bus portion;

a first memory module mounted in said first slot connector;

a second memory module mounted in said second slot connector; and

a flexible bridge connecting said first and second memory modules for providing a signal bus between said memory modules so that said first and second memory modules are serially connected between said first and second signal bus portions on said circuit board.

14. The memory system of claim 13 , wherein the memory modules are received in the respective slot connectors at a first side thereof and wherein the flexible bridge extends from a second side of the memory modules.

15. The memory system of claim 13 , wherein the flexible bridge comprises data lines and/or control signal lines for providing a data bus and/or a control signal bus between said memory modules.

16. The memory system of claim 13 further comprising a third slot connector and a fourth slot connector.

17. The memory system of claim 16 wherein said third and fourth slot connectors are located between said first and second slot connector.

18. The memory system of claim 16 , wherein the other end of said second signal bus portion is connected to said third slot connector and further comprising a third signal bus portion on said circuit board connected to said fourth slot connector;

a third memory module mounted in said third slot connector;

a fourth memory module mounted in said fourth slot connector;

another flexible bridge connecting said third and fourth memory modules to provide a signal bus between said third and fourth memory modules so that said third and fourth memory modular are serially connected between said second and third signal bus portions and so that said first, second, third, and fourth memory modules are serially connected between said first and third bus portions.

19. A memory system comprising:

a circuit board comprising a first slot connector and a second slot connector, each of said first and second slot connectors capable of receiving only a single memory module;

a first memory module mounted in said first slot connector;

a second memory module mounted in said second slot connector; and

a flexible bridge connecting said first and second memory module for providing a signal bus between said memory modules so that said first and second memory modules are serially connected between said first and second signal bus portions on said circuit board.