IP Library Granted Patent US 7,071,676
Granted Patent B2
US 7,071,676 · App. 10/681,498 · Granted Jul 4, 2006

Circuit configuration and method for measuring at least one operating parameter for an integrated circuit

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Quick Facts
Patent No.
US 7,071,676
App. No.
10/681,498
Granted
Jul 4, 2006
Kind
B2
Abstract

A circuit configuration for measuring at least one operating parameter for an integrated circuit includes an analysis circuit connected to at least one external connection on the integrated circuit. The analysis circuit detects a plurality of voltage level changes on the external connection, which is used to control a method of operation for the integrated circuit, in particular, and supplies them to a counter circuit that logs at least one digitally coded value. The coded value is, then, output for analysis purposes to ascertain at least one operating parameter. This, advantageously, allows an average mode of operation for the integrated circuit to be logged during operation of the circuit in the application using parameters and allows respective operating states to be ascertained.

Claims (51)

1. A circuit configuration for measuring at least one operating parameter for an integrated circuit, comprising:

a counter circuit logging at least one digitally coded value characterizing at least one operating parameter for specifying a mode of operation for the integrated circuit;

an analysis circuit to be connected to at least one external connection on the integrated circuit, said analysis circuit detecting a plurality of voltage level changes on the external connection and supplying the voltage level changes to said counter circuit; and

an output circuit connected to said analysis circuit, said output circuit externally outputting said at least one digitally coded value or a value derived therefrom.

2. The circuit configuration according to claim 1 , wherein the external connection is used to control a method of operation for the integrated circuit.

3. The circuit configuration according to claim 1 , wherein said counter circuit logs the voltage level changes over a defined period of time.

4. The circuit configuration according to claim 1 , wherein:

said analysis circuit is to be connected to a plurality of external connections on the integrated circuit; and

said counter circuit has a combinational logic circuit and is connected to the external connections through said combinational logic circuit.

5. The circuit configuration according to claim 4 , wherein:

said counter circuit has combinational logic circuits;

said analysis circuit is to be connected to a plurality of external connections on the integrated circuit and has a plurality of counter circuits; and

each of said counter circuits is to be connected to at least one of the external connections through a different one of said combinational logic circuits and respectively logs at least one digitally coded value.

6. The circuit configuration according to claim 1 , wherein:

said counter circuit has combinational logic circuits;

said analysis circuit is to be connected to a plurality of external connections on the integrated circuit and has a plurality of counter circuits; and

each of said counter circuits is to be connected to at least one of the external connections through a different one of said combinational logic circuits and respectively logs at least one digitally coded value.

7. The circuit configuration according to claim 4 , wherein said combinational logic circuit is one of hardwired and variably programmable.

8. The circuit configuration according to claim 1 , wherein:

said counter circuit is a plurality of counter circuits; and

each of said counter circuits has an associated register to which a content of a respective associated one of said counter circuits is copied and stored.

9. The circuit configuration according to claim 1 , wherein said counter circuit has an associated register to which a content of said counter circuit is copied and stored.

10. The circuit configuration according to claim 1 , wherein said analysis circuit has a time counter circuit connected to a clock signal connection for logging a defined period of time.

11. In an integrated circuit having modes of operation, at least one operating parameter, and at least one external connection, a circuit configuration for measuring the at least one operating parameter, comprising:

a counter circuit logging at least one digitally coded value characterizing the at least one operating parameter for specifying a mode of operation for the integrated circuit;

an analysis circuit connected to the at least one external connection, said analysis circuit detecting a plurality of voltage level changes on the external connection and supplying the voltage level changes to said counter circuit; and

an output circuit connected to said analysis circuit, said output circuit externally outputting said at least one digitally coded value or a value derived therefrom.

12. A method for measuring at least one operating parameter for an integrated circuit, which comprises:

detecting a plurality of voltage level changes on at least one external connection with an analysis circuit connected to the at least one external connection on the integrated circuit;

logging voltage level changes with the analysis circuit in a counter circuit utilizing at least one digitally coded value; and

outputting the coded value or a value derived from the coded value for purposes of analysis to ascertain at least one operating parameter for specifying a mode of operation for the integrated circuit.

13. The method according to claim 12 , which further comprises:

connecting the analysis circuit to a plurality of external connections on the integrated circuit;

detecting voltage level changes on the external connections in a plurality of different ways utilizing the analysis circuit;

logging the voltage level changes with the analysis circuit in a plurality of counter circuits utilizing respective digitally coded values; and

ascertaining a plurality of different operating parameters from the digitally coded values.

14. The method according to claim 12 , which further comprises:

providing the at least one external connection as a plurality of external connections on the integrated circuit;

providing the counter circuits as a plurality of counter circuits;

connecting the analysis circuit to the external connections;

utilizing the analysis circuit to detect voltage level changes on the external connections in a plurality of different ways and to log voltage level changes in the counter circuits using respective digitally coded values; and

ascertaining a plurality of different operating parameters from the digitally coded values.

15. The method according to claim 12 , which further comprises averaging the coded value or the value derived from the coded value.

16. The method according to claim 13 , which further comprises averaging the coded values.

17. The method according to claim 14 , which further comprises averaging the coded values.

18. The method according to claim 12 , which further comprises, upon reaching an averaging time that is a binary multiple during a measurement, relating the respective coded value logged up until the averaging time to the averaging time.

19. A method for measuring at least one operating parameter for an integrated circuit, which comprises:

connecting an analysis circuit to at least one external connection on the integrated circuit;

detecting a plurality of voltage level changes on the at least one external connection with the analysis circuit;

logging voltage level changes with the analysis circuit in a counter circuit utilizing at least one digitally coded value; and

subsequently outputting the coded value or a value derived from the coded value and analyzing the coded value or the value derived from the coded value to ascertain at least one operating parameter for specifying a mode of operation for the integrated circuit.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT 7105729 PREVIOUSLY RECORDED AT REEL: 036827 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 26, 2017
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 043336/0694 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036827/0885 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023796/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2006
From: PERNER, MARTIN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 017235/0812 →