Patent Assignment
Reel/Frame 043336/0694
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT 7105729 PREVIOUSLY RECORDED AT REEL: 036827 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
Recorded: 2017-07-26
Received: 2017-07-26
Pages: 18
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IEX, IRELAND
Covered Applications
(100)
METHOD FOR CLASSIFYING ERRORS IN THE LAYOUT OF A SEMICONDUCTOR CIRCUIT
App. No. 11/712,635
→
METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR SUBSTRATE COMPRISING A PLURALITY OF GATE STACKS ON A SEMICONDUCTOR SUBSTRATE, AND CORRESPONDING SEMICONDUCTOR STRUCTURE
App. No. 11/513,447
→
SIM CARD CONNECTOR WITH LOCKING ARRANGEMENT
App. No. 11/440,463
→
METHOD FOR CONTACTING PARTS OF A COMPONENT INTEGRATED INTO A SEMICONDUCTOR SUBSTRATE
App. No. 10/519,741
→
MEMORY DEVICE WITH COLUMN SELECT BEING VARIABLY DELAYED
App. No. 11/259,703
→
METHOD FOR PRODUCING PHASE SHIFTER MASKS
App. No. 11/252,476
→
PACKAGE FOR SEMICONDUCTOR COMPONENTS AND METHOD FOR PRODUCING THE SAME
App. No. 10/518,141
→
ELECTRONIC COMPONENT WITH MULTILAYERED REWIRING PLATE AND METHOD FOR PRODUCING THE SAME
App. No. 10/519,444
→
MRAM MEMORY CELL WITH A REFERENCE LAYER AND METHOD FOR FABRICATING
App. No. 10/509,553
→
METHOD FOR PURGING AN OPTICAL LENS
App. No. 11/127,304
→
METHOD FOR PRODUCING AN ANNULAR MICROSTRUCTURE ELEMENT
App. No. 11/112,743
→
PENTAARYLCYCLOPENTADIENYL UNITS AS ACTIVE UNITS IN RESISTIVE MEMORY ELEMENTS
App. No. 11/092,968
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COMPOSITION WHICH FORMS AN ELECTRICALLY CONDUCTIVE RESIST LAYER AND A METHOD FOR PATTERNING A PHOTORESIST USING THE RESIST LAYER
App. No. 11/087,729
→
SEMICONDUCTOR MEMORY WITH VERTICAL MEMORY TRANSISTORS AND METHOD FOR FABRICATING IT
App. No. 11/073,205
→
SEMICONDUCTOR MEMORY WITH VERTICAL MEMORY TRANSISTORS IN A CELL ARRAY ARRANGEMENT WITH 1-2F2 CELLS
App. No. 11/073,214
→
SONOS MEMORY CELLS AND ARRAYS AND METHOD OF FORMING THE SAME
App. No. 11/072,695
→
FABRICATION OF ORGANIC ELECTRONIC CIRCUITS BY CONTACT PRINTING TECHNIQUES
App. No. 11/066,550
→
SEMICONDUCTOR COMPONENT HAVING A CSP HOUSING
App. No. 11/061,762
→
METHOD FOR PRODUCING A PHASE MASK
App. No. 11/056,402
→
REDUCTION OF THE CONTACT RESISTANCE IN ORGANIC FIELD-EFFECT TRANSISTORS WITH PALLADIUM CONTACTS BY USING PHOSPHINES AND METAL-CONTAINING PHOSPHINES
App. No. 11/045,511
→
APPARATUS AND METHOD FOR PROCESSING WAFERS
App. No. 11/045,481
→
PROCESS FOR VERTICALLY PATTERNING SUBSTRATES IN SEMICONDUCTOR PROCESS TECHNOLOGY BY MEANS OF INCONFORMAL DEPOSITION
App. No. 11/042,326
→
METHOD FOR FABRICATING MICROCHIPS USING METAL OXIDE MASKS
App. No. 11/040,091
→
OCTUPOLAR MOLECULES USED AS ORGANIC SEMICONDUCTORS
App. No. 11/041,632
→
POLYMERIZABLE COMPOSITIONS; POLYMER, RESIST, AND LITHOGRAPHY METHOD
App. No. 10/520,534
→
REDUCING THE CONTACT RESISTANCE IN ORGANIC FIELD-EFFECT TRANSISTORS WITH PALLADIUM CONTACTS BY USING NITRILES AND ISONITRILES
App. No. 11/020,191
→
METHOD FOR FABRICATING AN NROM MEMORY CELL ARRAY
App. No. 11/023,041
→
RAM MEMORY CIRCUIT HAVING A PLURALITY OF BANKS AND AN AUXILIARY DEVICE FOR TESTING
App. No. 11/012,927
→
METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR SUBSTRATE COMPRISING A PLURALITY OF GATE STACKS ON A SEMICONDUCTOR SUBSTRATE, AND CORRESPONDING SEMICONDUCTOR STRUCTURE
App. No. 11/010,941
→
METHOD FOR FILLING TRENCH AND RELIEF GEOMETRIES IN SEMICONDUCTOR STRUCTURES
App. No. 11/010,186
→
METHOD FOR FABRICATING NROM MEMORY CELLS WITH TRENCH TRANSISTORS
App. No. 11/006,049
→
PHOTOSENSITIVE LACQUER FOR PROVIDING A COATING ON A SEMICONDUCTOR SUBSTRATE OR A MASK
App. No. 11/000,342
→
METHOD FOR THE PRODUCTION OF A MEMORY CELL, MEMORY CELL AND MEMORY CELL ARRANGEMENT
App. No. 10/999,810
→
MICROSCOPE ARRANGEMENT FOR INSPECTING A SUBSTRATE
App. No. 10/991,517
→
FLASH MEMORY CELL AND FABRICATION METHOD
App. No. 10/991,342
→
NON-VOLATILE FLASH SEMICONDUCTOR MEMORY AND FABRICATION METHOD
App. No. 10/991,345
→
GATE CONDUCTOR ISOLATION AND METHOD FOR MANUFACTURING SAME
App. No. 10/912,005
→
METHOD FOR FORMING A TOP OXIDE WITH NITRIDE LINER
App. No. 10/798,865
→
TEST STRUCTURE FOR IMPROVED VERTICAL MEMORY ARRAYS
App. No. 10/766,902
→
BUFFER AMPLIFIER ARCHITECTURE FOR SEMICONDUCTOR MEMORY CIRCUITS
App. No. 10/759,103
→
DEVICE ARCHITECTURE AND PROCESS FOR IMPROVED VERTICAL MEMORY ARRAYS
App. No. 10/748,332
→
ARRANGEMENT FOR THE PROTECTION OF THREE-DIMENSIONAL STRUCTURES ON WAFERS
App. No. 10/732,979
→
TRANSISTOR ARRAY AND SEMICONDUCTOR MEMORY CONFIGURATION FABRICATED WITH THE TRANSISTOR ARRAY
App. No. 10/718,310
→
POLYMER TRANSISTOR ARRANGEMENT, INTEGRATED CIRCUIT ARRANGEMENT AND METHOD FOR PRODUCING A POLYMER TRANSISTOR ARRANGEMENT
App. No. 10/714,536
→
METHOD FOR ALIGNING AND EXPOSING A SEMICONDUCTOR WAFER
App. No. 10/686,848
→
CIRCUIT CONFIGURATION AND METHOD FOR MEASURING AT LEAST ONE OPERATING PARAMETER FOR AN INTEGRATED CIRCUIT
App. No. 10/681,498
→
METHOD AND APPARATUS FOR INTERNALLY TRIMMING OUTPUT DRIVERS AND TERMINATIONS IN SEMICONDUCTOR DEVICES
App. No. 10/680,782
→
MEMORY CIRCUIT AND METHOD FOR READING OUT DATA
App. No. 10/676,596
→
INTEGRATED SEMICONDUCTOR CIRCUIT CONFIGURATION
App. No. 10/675,761
→
METHOD FOR THE PATTERNED, SELECTIVE METALLIZATION OF A SURFACE OF A SUBSTRATE
App. No. 10/675,634
→
CALIBRATION CONFIGURATION
App. No. 10/673,965
→
PHOTOSENSITIVE COATING MATERIAL FOR A SUBSTRATE AND PROCESS FOR EXPOSING THE COATED SUBSTRATE
App. No. 10/673,964
→
METHOD FOR CONTROLLING SEMICONDUCTOR CHIPS AND CONTROL APPARATUS
App. No. 10/672,145
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DEFECT REPAIR METHOD, IN PARTICULAR FOR REPAIRING QUARTZ DEFECTS ON ALTERNATING PHASE SHIFT MASKS
App. No. 10/668,375
→
PROCESS FOR DESIGNING AND MANUFACTURING SEMI-CONDUCTOR MEMORY COMPONENTS, IN PARTICULAR DRAM COMPONENTS
App. No. 10/668,684
→
CIRCUIT DEVICE WITH CLOCK PULSE DETECTION FACILITY
App. No. 10/668,683
→
PHOTOMASK, IN PARTICULAR ALTERNATING PHASE SHIFT MASK, WITH COMPENSATION STRUCTURE
App. No. 10/667,552
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ARRANGEMENT OF SEVERAL RESISTORS JOINTLY POSITIONED IN A WELL OF A SEMICONDUCTOR DEVICE, AND A SEMICONDUCTOR DEVICE INCLUDING AT LEAST ONE SUCH ARRANGEMENT
App. No. 10/663,354
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SEMICONDUCTOR DEVICE TESTING APPARATUS, SEMICONDUCTOR DEVICE TESTING SYSTEM, AND SEMICONDUCTOR DEVICE TESTING METHOD FOR MEASURING AND TRIMMING THE OUTPUT IMPEDANCE OF DRIVER DEVICES
App. No. 10/663,448
→
TEST STRUCTURE FOR MEASURING A JUNCTION RESISTANCE IN A DRAM MEMORY CELL ARRAY
App. No. 10/659,843
→
SEMI-CONDUCTOR COMPONENT WITH CLOCK RELAYING DEVICE
App. No. 10/658,741
→
FABRICATION METHOD FOR A SEMICONDUCTOR STRUCTURE HAVING A PARTLY FILLED TRENCH
App. No. 10/660,091
→
SYNCHRONIZATION DEVICE FOR A SEMICONDUCTOR MEMORY DEVICE
App. No. 10/659,693
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METHOD FOR DETERMINING THE END POINT FOR A CLEANING ETCHING PROCESS
App. No. 10/656,353
→
METHOD FOR THE SOLDER-STOP STRUCTURING OF ELEVATIONS ON WAFERS
App. No. 10/656,042
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MASK FOR PROJECTING A STRUCTURE PATTERN ONTO A SEMICONDUCTOR SUBSTRATE
App. No. 10/653,537
→
BARRRIER LAYER AND A METHOD FOR SUPPRESSING DIFFUSION PROCESSES DURING THE PRODUCTION OF SEMICONDUCTOR DEVICES
App. No. 10/653,599
→
METHOD FOR PATTERNING A MASK LAYER AND SEMICONDUCTOR PRODUCT
App. No. 10/653,589
→
METHOD AND CONFIGURATION FOR COMPENSATING FOR UNEVENNESS IN THE SURFACE OF A SUBSTRATE
App. No. 10/652,291
→
INTEGRATED MEMORY AND METHOD FOR SETTING THE LATENCY IN THE INTEGRATED MEMORY
App. No. 10/649,408
→
SEMICONDUCTOR MEMORY APPARATUS WITH VARIABLE CONTACT CONNECTIONS AND A CORRESPONDING SEMICONDUCTOR APPARATUS
App. No. 10/646,166
→
SHIFT REGISTER CHAIN FOR TRIMMING GENERATORS FOR AN INTEGRATED SEMICONDUCTOR APPARATUS
App. No. 10/645,053
→
METHOD FOR FABRICATING CONNECTION REGIONS OF AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT HAVING CONNECTION REGIONS
App. No. 10/642,092
→
METHOD OF PRODUCING A SEMICONDUCTOR COMPONENT HAVING A COMPLIANT BUFFER LAYER
App. No. 10/642,063
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PHASE DETECTOR
App. No. 10/640,230
→
INTEGRATED CIRCUIT AND METHOD FOR PRODUCING A COMPOSITE COMPRISING A TESTED INTEGRATED CIRCUIT AND AN ELECTRICAL DEVICE
App. No. 10/637,899
→
METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE AND CORRESPONDING SEMICONDUCTOR DEVICE
App. No. 10/634,242
→
INTEGRATED MEMORY AND METHOD FOR CHECKING THE FUNCTIONING OF AN INTEGRATED MEMORY
App. No. 10/633,996
→
REFLECTIVE MIRROR FOR LITHOGRAPHIC EXPOSURE AND PRODUCTION METHOD
App. No. 10/632,752
→
METHOD FOR TESTING A SEMICONDUCTOR MEMORY HAVING A PLURALITY OF MEMORY BANKS
App. No. 10/631,356
→
MICROELECTRONIC PROCESS AND STRUCTURE
App. No. 10/631,587
→
SEMICONDUCTOR TRENCH STRUCTURE
App. No. 10/630,373
→
SEMICONDUCTOR CIRCUIT STRUCTURE AND METHOD FOR FABRICATING THE SEMICONDUCTOR CIRCUIT STRUCTURE
App. No. 10/626,957
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INTEGRATED SYNCHRONOUS MEMORY AND MEMORY CONFIGURATION HAVING A MEMORY MODULE WITH AT LEAST ONE SYNCHRONOUS MEMORY
App. No. 10/626,955
→
CIRCUIT CONFIGURATION FOR READING OUT A PROGRAMMABLE LINK
App. No. 10/627,841
→
POLYMERIZABLE COMPOSITION, POLYMER, RESIST, AND PROCESS FOR ELECTRON BEAM LITHOGRAPHY
App. No. 10/627,906
→
METHOD FOR CONNECTING AN INTEGRATED CIRCUIT TO A SUBSTRATE AND CORRESPONDING CIRCUIT ARRANGEMENT
App. No. 10/625,495
→
CIRCUIT AND METHOD FOR WRITING AND READING DATA FROM A DYNAMIC MEMORY CIRCUIT
App. No. 10/623,831
→
METHOD OF GENERATING A TEST PATTERN FOR SIMULATING AND/OR TESTING THE LAYOUT OF AN INTEGRATED CIRCUIT
App. No. 10/623,067
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WAFER LIFTING DEVICE
App. No. 10/622,050
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METHOD FOR CORRECTING LOCAL LOADING EFFECTS IN THE ETCHING OF PHOTOMASKS
App. No. 10/621,535
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CONFIGURATION AND METHOD FOR CHECKING AN ADDRESS GENERATOR
App. No. 10/620,587
→
PVD METHOD AND PVD APPARATUS
App. No. 10/620,570
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CIRCUIT ELEMENT WITH TIMING CONTROL
App. No. 10/620,092
→
CIRCUIT CONFIGURATION FOR THE BIT-PARALLEL OUTPUTTING OF A DATA WORD
App. No. 10/619,290
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INTEGRATED SEMICONDUCTOR MEMORY AND FABRICATION METHOD
App. No. 10/619,970
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INTEGRATED MEMORY AND METHOD FOR TESTING THE MEMORY
App. No. 10/619,157
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CIRCUIT CONFIGURATION FOR CONTROLLING LOAD-DEPENDENT DRIVER STRENGTHS
App. No. 10/619,014
→
TEST CIRCUIT AND METHOD FOR TESTING AN INTEGRATED MEMORY CIRCUIT
App. No. 10/613,367
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LEVEL SHIFTER WITHOUT DUTYCYCLE DISTORTION
App. No. 10/613,381
→