IP Library Granted Patent US 7,087,512
Granted Patent B2
US 7,087,512 · App. 10/642,092 · Granted Aug 8, 2006

Method for fabricating connection regions of an integrated circuit, and integrated circuit having connection regions

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Quick Facts
Patent No.
US 7,087,512
App. No.
10/642,092
Granted
Aug 8, 2006
Kind
B2
Abstract

A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.

Claims (25)

1. A method comprising

providing an integrated circuit having a connection region,

applying a dielectric to the integrated circuit,

applying a metallization layer to the dielectric, the metallization layer being corrodible,

applying a conductive protection device that is wetable by the liquid solder to the metallization layer,

patterning the conductive protection device such that the protection device is removed an area around the connection region; and

oxidizing the metallization layer in the areas around the connection region thereby forming a solder stop device that is not wetable by the liquid solder.

2. The method of claim 1 , further comprising

applying a connection device to the connection region.

3. The method of claim 2 , wherein applying the connection device includes applying a solder ball.

4. The method of claim 1 , further comprising

applying a carrier layer to the dielectric.

5. The method of claim 4 , further comprising selecting

a sputtering process for applying the carrier layer.

6. The method of claim 1 , further comprising

applying an interconnect layer, and applying a barrier device to the dielectric.

7. The method of claim 6 , wherein

applying the interconnect layer comprises electrochemically depositing the interconnect layer.

8. The method of claim 1 , further comprising

patterning the metallization layer before applying the protection device.

9. The method of claim 1 , further comprising

electrochemically depositing the protection device.

10. The method of claim 1 , further comprising

providing a patterned photomask, and

etching the protection device in a region exposed by the photomask.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT 7105729 PREVIOUSLY RECORDED AT REEL: 036827 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 26, 2017
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 043336/0694 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036827/0885 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023796/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2004
From: HEDLER, HARRY; IRSIGLER, ROLAND; MEYER, THORSTEN; VASQUEZ, BARBARA
To: INFINEON TECHNOLOGIES AG
Reel/Frame 014878/0307 →