Calibration configuration
View Patent ↗A calibration configuration for setting an adjustable impedance has a voltage divider with a variable resistor and a resistor connected in series, which circuit is supplied with potentials of a supply voltage and has, between the resistors, a partial voltage tap off terminal. A circuit has a further resistor, whose value is in a fixed relationship with a resistance of the first voltage divider resistor, and generates a voltage dependent upon a value derived from the further resistor. The voltage and the partial voltage are fed to a comparator for outputting a comparison result to a downstream control logic unit, which logic unit is coupled to the resistor of the first voltage divider and generates a control signal dependent upon the comparator output signal. The control logic unit control signal is used to set the variable resistor until the voltages fed to the comparator correspond to one another.
1. A calibration configuration, comprising:
a first voltage divider having:
a variable resistor and a resistor connected in series and defining a terminal therebetween for tapping off a partial voltage between said variable resistor and said resistor;
a positive terminal connected to said variable resistor for feeding in a positive supply potential of a supply voltage; and
a negative terminal connected to said resistor for feeding in a negative supply potential of the supply voltage;
a circuit configuration having:
an output terminal for providing a voltage;
a further resistor having a value in a fixed relationship with a resistance of said resistor of said first voltage divider;
an evaluation device connected to said further resistor and generating a control signal dependent upon a value derived from said further resistor; and
a voltage generator connected to said evaluation device and generating said voltage from a multiplicity of possible voltages in a manner dependent on said control signal;
a comparator having:
a first input connected to said output terminal of said circuit configuration for feeding in said voltage;
a second input connected to said terminal for tapping off said partial voltage; and
an output terminal for outputting a comparison result of a comparison of said voltage and said partial voltage respectively fed in at said first input and at said second input; and
a control logic unit connected downstream of said comparator with respect to an input-to-output direction of said comparator, said control logic unit:
having an output terminal coupled to said variable resistor of said first voltage divider; and
generating, dependent upon said comparison result, a control signal at said output terminal driving said variable resistor.
2. The calibration configuration according to claim 1 , wherein:
said circuit configuration has:
an input terminal for feeding in a reference current; and
a terminal for tapping off a voltage across said further resistor, said terminal being connected to said input terminal and to said further resistor and a voltage dependent upon the reference current being tapped off at said terminal; and
said evaluation device:
is connected to said terminal for tapping off said voltage across said further resistor; and
has an output terminal for tapping off said control signal therefrom.
3. The calibration configuration according to claim 2 , wherein:
said evaluation device has a combination element connected to said further resistor through said terminal for tapping off said voltage across said further resistor; and said combination element has a further terminal for feeding in:
values representing the supply potentials of the supply voltage;
a value representing a target impedance of said variable resistor to be set; and
a value representing the reference current.
4. The calibration configuration according to claim 3 , wherein:
said combination element produces an output signal;
said evaluation device has an analog-to-digital converter downstream of said combination element with respect to an input-to-output direction of said evaluation device; and
said analog-to-digital converter converts said output signal of said combination element into a control signal output at said output terminal of said evaluation device.
5. The calibration configuration according to claim 3 , wherein:
said combination element is programmed to carry out the calculation:/R*Icopy+Vrefcopy) where:
Vrefcopy corresponds to said voltage across said further resistor;
V corresponds to a supply voltage to be fed to said first voltage divider;
R corresponds to said variable resistor of said first voltage divider; and
Icopy corresponds to said reference current of said circuit configuration.
6. The calibration configuration according to claim 1 , wherein said circuit configuration has a voltage generator with a multiplexer and a further voltage divider, said voltage generator is connected downstream of said evaluation device with respect to an input-to-output direction of said evaluation device, said multiplexer, dependent upon said control signal output by said evaluation device, selecting a voltage from a plurality of voltages provided by said further voltage divider and providing said selected voltage as said voltage at said output terminal.
7. The calibration configuration according to claim 6 , wherein said further voltage divider:
is a resistor network having a multiplicity of resistors connected in series; and
has at least one intermediate tap for tapping off said voltage at said output terminal.
8. The calibration configuration according to claim 7 , wherein:
said at least one intermediate tap is a plurality of taps;
said control signal of said evaluation device drives said multiplexer; and
said multiplexer couples one of said taps to said output terminal dependent upon said output signal.
9. The calibration configuration according to claim 1 , which further comprises an output driver having at least two field-effect transistors of complementary channel types, said at least two field-effect transistors having drain-source paths connected in series, said variable resistor being formed by at least one of said field-effect transistors.
10. The calibration configuration according to claim 9 , which further comprises:
at least one further field-effect transistor respectively connected in parallel with said at least two field-effect transistors;
said gate terminals of said at least one field-effect transistor being connected to said output terminal of said control logic unit for feeding said control signal to disconnect or connect said at least one further field-effect transistor.
11. In an integrated semiconductor chip, a monolithically integrated calibration configuration, comprising:
a first voltage divider having:
a variable resistor and a resistor connected in series and defining a terminal therebetween for tapping off a partial voltage between said variable resistor and said resistor;
a positive terminal connected to said variable resistor for feeding in a positive supply potential of a supply voltage; and
a negative terminal connected to said resistor for feeding in a negative supply potential of the supply voltage;
a circuit configuration having:
an output terminal for providing a voltage;
a further resistor having a value in a fixed relationship with a resistance of said resistor of said first voltage divider;
an evaluation device connected to said further resistor and generating a control signal dependent upon a value derived from said further resistor; and
a voltage generator connected to said evaluation device and generating said voltage from a multiplicity of possible voltages in a manner dependent on said control signal;
a comparator having:
a first input connected to said output terminal of said circuit configuration for feeding in said voltage;
a second input connected to said terminal for tapping off said partial voltage; and
an output terminal for outputting a comparison result of a comparison of said voltage and said partial voltage respectively fed in at said first input and at said second input; and
a control logic unit connected downstream of said comparator with respect to an input-to-output direction of said comparator, said control logic unit:
having an output terminal coupled to said variable resistor of said first voltage divider; and
generating, dependent upon said comparison result, a control signal at said output terminal driving said variable resistor.
12. A calibration configuration, comprising:
a semiconductor chip having a monolithically integrated first voltage divider and a monolithically integrated comparator;
an automatic test device not disposed on said semiconductor chip for testing said semiconductor chip, said automatic test device having an evaluation device;
said first voltage divider having:
a variable resistor and a resistor connected in series and defining a terminal therebetween for tapping off a partial voltage between said variable resistor and said resistor;
a positive terminal connected to said variable resistor for feeding in a positive supply potential of a supply voltage; and
a negative terminal connected to said resistor for feeding in a negative supply potential of the supply voltage;
a circuit configuration having:
an output terminal for providing a voltage;
a further resistor having a value in a fixed relationship with a resistance of said resistor of said first voltage divider;
said evaluation device connected to said further resistor and generating a control signal dependent upon a value derived from said further resistor; and
a voltage generator connected to said evaluation device and generating said voltage from a multiplicity of possible voltages in a manner dependent on said control signal;
said comparator having:
a first input connected to said output terminal of said circuit configuration for feeding in said voltage;
a second input connected to said terminal for tapping off said partial voltage; and
an output terminal for outputting a comparison result of a comparison of said voltage and said partial voltage respectively fed in at said first input and at said second input; and
a control logic unit connected downstream of said comparator with respect to an input-to-output direction of said comparator, said control logic unit:
having an output terminal coupled to said variable resistor of said first voltage divider; and
generating, dependent upon said comparison result, a control signal at said output terminal driving said variable resistor.
13. A calibration configuration, comprising:
a first voltage divider having:
a variable resistor and a resistor connected in series and defining a terminal therebetween for tapping off a partial voltage between said variable resistor and said resistor;
a positive terminal connected to said variable resistor for feeding in a positive supply potential of a supply voltage; and
a negative terminal connected to said resistor for feeding in a negative supply potential of the supply voltage;
a circuit configuration having:
an output terminal for providing a voltage;
a further resistor having a value in a fixed relationship with a resistance of said resistor of said first voltage divider;
an evaluation device connected to said further resistor and generating a control signal dependent upon a value derived from said further resistor; and
a voltage generator connected to said evaluation device and generating said voltage from a multiplicity of possible voltages in a manner dependent on said control signal;
a comparator having:
a first input connected to said output terminal of said circuit configuration for feeding in said voltage;
a second input connected to said terminal for tapping off said partial voltage; and
an output terminal for outputting a comparison result of a comparison of said voltage and said partial voltage respectively fed in at said first input and at said second input; and
a control logic unit connected to said output terminal of said comparator, said control logic unit:
having an output terminal coupled to said variable resistor of said first voltage divider; and
generating, dependent upon said comparison result, a control signal at said output terminal driving said variable resistor.
14. The calibration configuration according to claim 13 , wherein:
said circuit configuration has:
an input terminal for feeding in a reference current; and
a terminal for tapping off a voltage across said further resistor, said terminal being connected to said input terminal and to said further resistor and a voltage dependent upon the reference current being tapped off at said terminal; and
said evaluation device:
is connected to said terminal for tapping off said voltage across said further resistor; and
has an output terminal for tapping off said control signal therefrom.
15. The calibration configuration according to claim 14 , wherein:
said evaluation device has a combination element connected to said further resistor through said terminal for tapping off said voltage across said further resistor; and
said combination element has a further terminal for feeding in:
values representing the supply potentials of the supply voltage;
a value representing a target impedance of said variable resistor to be set; and
a value representing the reference current.
16. The calibration configuration according to claim 15 , wherein:
said combination element produces an output signal at an output;
said evaluation device has an analog-to-digital converter connected to said output of said combination element; and
said analog-to-digital converter converts said output signal of said combination element into a control signal output at said output terminal of said evaluation device.
17. The calibration configuration according to claim 13 , wherein:
said evaluation device has an output terminal for tapping off said control signal therefrom; and
said circuit configuration has a voltage generator with a multiplexer and a further voltage divider, said voltage generator is connected to said output terminal of said evaluation device, said multiplexer, dependent upon said control signal output by said evaluation device, selecting a voltage from a plurality of voltages provided by said further voltage divider and providing said selected voltage as said voltage at said output terminal.