Circuit device with clock pulse detection facility

1. A circuit device ( 1 ), comprising at least a first connection ( 3 a ) and a second connection ( 3 b ), adapted to receive a single clock pulse (CLK, CLK T ) at the first connection ( 3 a ), and adapted—alternatively to the single clock pulse (CLK, CLK T )—to receive a differential clock pulse (CLK, CLK T , /CLK, /CLK T ) at the first and second connections ( 3 a , 3 b ), and a detection facility ( 2 ) to detect which kind of clock pulse (CLK, CLK T ), (CLK, CLK T , /CLK, /CLK T ) is received, the detection facility ( 2 ) having a first state, if a differential clock pulse (CLK, CLK T , /CLK, /CLK T ) is received at the first and second connections ( 3 a , 3 b ), in which a first output signal is provided, and a second state, if a single clock pulse (CLK, CLK T ) is received at the first connection ( 3 a ), in which a second output signal different than the first output signal is provided.

2. A circuit device ( 1 ) comprising:

at least a first connection ( 3 a ), to which a clock pulse (CLK, CLK T ) can be applied, and a second connection ( 3 b ), to which a clock pulse (/CLK, /CLK T ) can be applied;

a detection facility ( 2 ) which in determining whether a clock pulse (/CLK, /CLK T ) is present at the second connection ( 3 b ), determines whether there are differential clock pulses (CLK, CLK T ; /CLK, /CLK T ) present at the connections ( 3 a , 3 b ), or whether there is a single clock pulse (CLK, CLK T ) present at the first connection ( 3 a ), but not at the second connection ( 3 b );

a comparison device ( 24 ) for comparing the signal present at the connection ( 3 b ), in particular the clock pulse (/CLK, /CLK T ) applied thereto, with a reference signal (VREF); and

a counter device ( 7 ), in particular for detecting the number of pulses, particularly clock pulse detection signals, emitted by the comparison device ( 24 ).

3. A circuit device ( 1 ) according to claim 2 , in which the comparison device ( 24 ) comprises a differential amplifier.

4. A circuit device ( 1 ) according to claim 2 , in which the comparison device ( 24 ) emits a pulse, more specifically a clock pulse detection signal, when the level of the signal present at the connection ( 3 b ) exceeds or falls below a predetermined level (VREF), in particular, the level of the reference signal (VREF).

5. A circuit device ( 1 ) according to claim 2 , in which the comparison device ( 24 ) emits a signal, more specifically a clock pulse detection signal, when the level of the signal present at the connection ( 3 b ) first exceeds a predetermined, first level (VREF+ΔU 1 ), and then falls below a predetermined second level (VREF−ΔU 2 ) that differs from the first level.

6. A circuit device ( 1 ) according to claim 2 , in which the comparison device ( 24 ) then emits a pulse, more specifically a clock pulse detection signal, when the level of the signal present at the connection ( 3 b ) first falls below a predetermined first level and then exceeds a predetermined second level that differs from the first level.

7. A circuit device ( 1 ) according to claim 2 , in which, when the number (Z) of pulse, in particular clock pulse detection signals emitted by the comparison device ( 24 ), and detected by the counter device ( 7 ), is larger then or equal to a predetermined number (Z 0 ), it is determined that the clock pulse (/CLK, /CLK T ) is present at the connection ( 3 b ).

8. A semi-conductor component that comprises at least one circuit device ( 1 ) comprising:

at least a first connection ( 3 a ) and a second connection ( 3 b ), adapted to receive a single clock pulse (CLK, CLK T ) at the first connection ( 3 a ) and adapted—alternatively to the single clock pulse (CLK, CLK T )—to receive a differential clock pulse (CLK, CLK T ; /CLK, /CLK T ) at the first and second connections ( 3 a , 3 b ); and

a detection facility ( 2 ) to detect which kind of clock pulse (CLK, CLK T ), (CLK, CLK T ; /CLK, /CLK T ) is received,

the detection facility ( 2 ) having a first state, if differential clock pulses (CLK, CLK T ; /CLK, /CLK T ) are received at the connections ( 3 a , 3 b ), in which a first output signal is provided, and a second state, if a single clock pulse (CLK, CLK T ) is received at the first connection ( 3 a ), in which a second output signal different than the first output signal is provided.

9. A semi-conductor component according to claim 8 , which is a DDR (double data rate) component, in particular a DDR memory component.

10. A semi-conductor component according to claim 8 , in which the memory component is a DRAM (dynamic random access memory).