IP Library Granted Patent US 6,891,431
Granted Patent B2
US 6,891,431 · App. 10/675,761 · Granted May 10, 2005

Integrated semiconductor circuit configuration

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Quick Facts
Patent No.
US 6,891,431
App. No.
10/675,761
Granted
May 10, 2005
Kind
B2
Abstract

To measure the current consumption of a circuit device with a current measuring device, the circuit device being supplied by a current/voltage supply line device, as simply as possible without the need for additional measuring devices, an integrated circuit configuration includes integrating the circuit configuration, the current measuring device, and, also, the current/voltage supply line device in a common chip and forming the current measuring device with a Hall sensor device.

Claims (38)

1. An integrated semiconductor circuit configuration, comprising:

at least one of a semiconductor material region and a chip;

a circuit device having a current consumption;

a current/voltage supply line device connected to said circuit device;

a current measuring device connected to said current/voltage supply line device for measuring the current consumption of said circuit device through said current/voltage supply line device, said current measuring device having at least one Hall sensor device; and

said circuit device, said current measuring device, and at least part of said current/voltage supply line device being commonly integrated in said at least one of said semiconductor material region and said chip.

2. The integrated semiconductor circuit configuration according to claim 1 , wherein said Hall sensor device measures an electric current flowing in a respective current/voltage supply line device through a magnetic field generated by the current.

3. The integrated semiconductor circuit configuration according to claim 1 , wherein:

said Hall sensor device has a plurality of Hall sensors sensing a plurality of at most partly overlapping measurement ranges; and

one of said Hall sensors is for one measurement range.

4. The integrated semiconductor circuit configuration according to claim 3 , wherein:

at least one of said Hall sensor device and each of said Hall sensors has a magnetic field concentrating device concentrating a magnetic field arising as a result of current flow in said current/voltage supply line device onto said at least one of said Hall sensor device and said each of said Hall sensors.

5. The integrated semiconductor circuit configuration according to claim 4 , wherein said magnetic field concentrating device has a soft-magnetic material.

6. The integrated semiconductor circuit configuration according to claim 4 , wherein said magnetic field concentrating device substantially encloses a cross-section of a respective one of said current/voltage supply line devices at at least one location.

7. The integrated semiconductor circuit configuration according to claim 4 , wherein:

said magnetic field concentrating device has a gap; and

said at least one of said Hall sensor device and a respective one of said Hall sensors is disposed in a region of said gap.

8. The integrated semiconductor circuit configuration according to claim 4 , wherein said Hall sensor device is configured as one of a compensation current converter and a closed-loop Hall transducer.

9. The integrated semiconductor circuit configuration according to claim 8 , further comprising a magnetic field compensation device.

10. The integrated semiconductor circuit configuration according to claim 9 , wherein said magnetic field compensation device is a current line device in a region of said magnetic field concentrating device.

11. The integrated semiconductor circuit configuration according to claim 1 , wherein said Hall sensor device is formed in a semiconductor material.

12. The integrated semiconductor circuit configuration according to claim 1 , wherein said semiconductor material is silicon.

13. The integrated semiconductor circuit configuration according to claim 1 , further comprising a compensation device adapted to compensate for a voltage drop of an operating voltage occurring across said Hall sensor device during operation.

14. The integrated semiconductor circuit configuration according to claim 1 , further comprising two output terminals tapping off a Hall voltage of said Hall sensor device for externally measuring the Hall voltage and, thereby, externally measuring current flowing through said current/voltage supply line device.

15. The integrated semiconductor circuit configuration according to claim 1 , wherein said current measuring device internally measures a Hall voltage of said Hall sensor device and, thereby, internally measures current flowing through said current/voltage supply line device.

16. The integrated semiconductor circuit configuration according to claim 15 , further comprising:

a comparison voltage terminal receiving an externally fed in comparison voltage for the internal current measurement of the Hall voltage measurement; and

a comparison device connected to said comparison voltage terminal and to said Hall sensor device for feeding in the comparison voltage of said comparison voltage terminal and the Hall voltage of said Hall sensor device, said comparison device comparing the Hall voltage with the comparison voltage.

17. The integrated semiconductor circuit configuration according to claim 16 , further comprising a register storing therein one of data and signals representative of the current flowing in said current/voltage supply line device, said register providing at least one of said data and signals for reading out therefrom.

18. The integrated semiconductor circuit configuration according to claim 1 , further comprising a register storing therein one of data and signals representative of the current flowing in said current/voltage supply line device, said register providing at least one of said data and signals for reading out therefrom.

19. The integrated semiconductor circuit configuration according to claim 17 , further comprising at least one input/output terminal connected to said register for at least one of writing to and reading from said register.

20. The integrated semiconductor circuit configuration according to claim 18 , further comprising at least one input/output terminal connected to said register for at least one of writing to and reading from said register.

21. An integrated semiconductor circuit configuration, comprising:

at least one of a semiconductor material region and a chip;

a current/voltage supply line device having a current consumption;

a current measuring device being connected to said current/voltage supply line device and having at least one Hall sensor device for measuring the current consumption through said current/voltage supply line device;

a circuit device connected to said current/voltage supply line device and supplied at least one of current and voltage through said current/voltage supply line device, and

said circuit device, said current measuring device and at least part of said current/voltage supply line device being commonly integrated in said at least one of said semiconductor material region and said chip.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT 7105729 PREVIOUSLY RECORDED AT REEL: 036827 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 26, 2017
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 043336/0694 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036827/0885 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023796/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2005
From: BEER, PETER; OHLHOFF, CARSTEN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 016429/0767 →