Semiconductor memory with vertical memory transistors and method for fabricating it
View Patent ↗The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.
1. A semiconductor memory having a multiplicity of memory cells, each of the memory cells comprising:
a semiconductor layer arranged on a substrate, a semiconductor surface of said semiconductor layer having at least one step between a deeper semiconductor region and a higher semiconductor region that is higher in a direction normal to the substrate;
at least one conductively doped deeper contact region formed in the deeper semiconductor region, and a conductively doped higher contact region formed in the higher semiconductor region;
at least one channel region extending in the semiconductor layer between the deeper contact region and the higher contact region;
at least one electrically insulating trapping layer designed for trapping and emitting charge carriers, the trapping layer being arranged on a gate oxide layer adjoining the channel region; and
at least one gate electrode for controlling the electrical conductivity of the channel region, the gate electrode adjoining, in a first region, a control oxide layer arranged on the trapping layer and, in a second region, the gate oxide layer arranged on the channel region.
2. The semiconductor memory of claim 1 , wherein the surface regions of the deeper semiconductor region and of the higher semiconductor region run essentially parallel to a plane of the substrate.
3. The semiconductor memory of claim 2 , wherein the surface region of the higher semiconductor region forms a surface of the higher contact region.
4. The semiconductor memory of claim 1 , wherein each of the memory cells comprise a multiplicity of the deeper contact regions and one of the higher contact regions and one of the channel regions extending between each of the deeper contact regions and the higher contact region.
5. The semiconductor memory of claim 4 , wherein the higher semiconductor region comprises, in a section running parallel to a plane of the substrate, an essentially rectangular configuration with four side edges and each of the side edges being assigned precisely one of the deeper contact regions.
6. The semiconductor memory of claim 1 , wherein the surface regions of the deeper semiconductor region and of the higher semiconductor region are connected by a step side area of the step, which runs essentially perpendicular to a substrate plane.
7. The semiconductor memory of claim 6 , wherein the trapping layer is spaced apart from the step side area and the surface region of the deeper semiconductor region by the gate oxide layer.
8. The semiconductor memory of claim 1 , wherein the deeper contact region extends as far as a step side area of the step.
9. The semiconductor memory of claim 1 , wherein the trapping layer comprises silicon nitride.
10. A semiconductor memory having a multiplicity of memory cells, each of the memory cells comprising:
a semiconductor layer arranged on a substrate, a semiconductor surface of said semiconductor layer having at least one step between a deeper semiconductor region and a higher semiconductor region that is higher in a direction normal to the substrate;
at least one conductively doped deeper contact region formed in the deeper semiconductor region, and a conductively doped higher contact region formed in the higher semiconductor region, wherein each of the memory cells comprise one or more of the deeper contact regions and one of the higher contact regions and one of the channel regions extending between each of the deeper contact regions and the higher contact region;
at least one channel region extending in the semiconductor layer between the deeper contact region and the higher contact region;
at least one electrically insulating trapping layer designed for trapping and emitting charge carriers, the trapping layer being arranged on a gate oxide layer adjoining the channel region; and
at least one gate electrode for controlling the electrical conductivity of the channel region, the gate electrode adjoining, in a first region, a control oxide layer arranged on the trapping layer and, in a second region, the gate oxide layer arranged on the channel region.
11. The semiconductor memory of claim 10 , wherein the surface regions of the deeper semiconductor region and of the higher semiconductor region run essentially parallel to a plane of the substrate.
12. The semiconductor memory of claim 11 , wherein the surface region of the higher semiconductor region forms a surface of the higher contact region.
13. The semiconductor memory of claim 10 , wherein the higher semiconductor region comprises, in a section running parallel to a plane of the substrate, an essentially rectangular configuration with four side edges and each of the side edges being assigned precisely one of the deeper contact regions.
14. The semiconductor memory of claim 10 , wherein the surface regions of the deeper semiconductor region and of the higher semiconductor region are connected by a step side area of the step, which runs essentially perpendicular to a substrate plane.
15. The semiconductor memory of claim 14 , wherein the trapping layer is spaced apart from the step side area and the surface region of the deeper semiconductor region by the gate oxide layer.
16. The semiconductor memory of claim 10 , wherein the deeper contact region extends as far as a step side area of the step.
17. The semiconductor memory of claim 10 , wherein the trapping layer comprises silicon nitride.