IP Library Granted Patent US 6,867,137
Granted Patent B2
US 6,867,137 · App. 10/660,091 · Granted Mar 15, 2005

Fabrication method for a semiconductor structure having a partly filled trench

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Quick Facts
Patent No.
US 6,867,137
App. No.
10/660,091
Granted
Mar 15, 2005
Kind
B2
Abstract

The present invention provides a fabrication method for a semiconductor structure having a partly filled trench, having the following steps: provision of a semiconductor structure ( 1, 5 ) having a trench ( 2 ); filling of the trench ( 2 ) with a filling ( 10 ) in such a way that the filling ( 10 ) projects above a surface (OF) of the semiconductor structure ( 1, 5 ) by a first height (h1), the filling ( 10 ) covering the trench ( 2 ) and the periphery ( 20 ) of the trench ( 2 ); planarization of the filling ( 10 ) in a first etching step in such a way that the filling ( 10 ) is essentially planar with the surface (OF) of the semiconductor structure ( 1, 5 ); and sinking of the filling ( 10 ) in the trench ( 2 ) in a second etching step by a predetermined depth (T) proceeding from the surface of the semiconductor structure ( 1, 5 ); essentially the same plasma power and the same etchant composition being used for the first and second etching steps.

Claims (20)

1. Fabrication method for a semiconductor structure having a partly filled trench, having the following steps:

(a) provision of a semiconductor structure having a trench;

(b) filling of the trench with a filling in such a way that the filling projects above a surface of the semiconductor structure by a first height, the filling covering the trench and the periphery of the trench;

(c) planarization of the filling in a first etching step in such a way that the filling is essentially planar with the surface of the semiconductor structure;

(d) sinking of the filling in the trench in a second etching step by a predetermined depth proceeding from the surface of the semiconductor structure;

(e) essentially the same plasma power and the same etchant composition being used for the first and second etching steps; and

(f) wherein a planarization of the filling is carried out in a zeroth etching step before the first etching step in such a way that the filling projects above the surface of the semiconductor structure by a second height, the filling covering the trench and the periphery of the trench, the zeroth etching step having a higher etching rate than the first etching step.

2. Method according to claim 1 , wherein essentially the same etchant composition as for the first and second etching steps but an increased plasma power are used for the zeroth etching step.

3. Method according to claim 1 , wherein at least the first etching step is carried out with a first time duration which is determined by an end point identification.

4. Method according to claim 1 , wherein the zeroth etching step and the second etching step are carried out with a predetermined zeroth and second time duration.

5. Method according to claim 1 , wherein the second etching step is carried out with a second time duration which is determined by an end point identification.

6. Method according to claim 1 , wherein the semiconductor structure comprises a semiconductor substrate and a mask situated thereon, the mask being used for the etching of the trench.

7. Method according to claim 3 , wherein the end point identification is carried out by interferometry.

8. Fabrication method for a semiconductor structure having a partly filled trench, having the following steps:

(a) provision of a semiconductor structure having a trench;

(b) filling of the trench with a filling in such a way that the filling projects above a surface of the semiconductor structure by a first height, the filling covering the trench and the periphery of the trench;

(c) planarization of the filling in a first etching step in such a way that the filling is essentially planar with the surface of the semiconductor structure;

(d) sinking of the filling in the trench in a second etching step by a predetermined depth proceeding from the surface of the semiconductor structure;

(e) essentially the same plasma power and the same etchant composition being used for the first and second etching steps; and

(f) wherein the etchant composition contains SF 6 , Ar and Cl 2 .

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT 7105729 PREVIOUSLY RECORDED AT REEL: 036827 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 26, 2017
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 043336/0694 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036827/0885 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023796/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2003
From: HANSEL, JANA; RUDOLPH, MATTHIAS
To: INFINEON TECHNOLOGIES AG
Reel/Frame 014071/0114 →