IP Library Granted Patent US 7,056,628
Granted Patent B2
US 7,056,628 · App. 10/653,537 · Granted Jun 6, 2006

Mask for projecting a structure pattern onto a semiconductor substrate

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Quick Facts
Patent No.
US 7,056,628
App. No.
10/653,537
Granted
Jun 6, 2006
Kind
B2
Abstract

A mask is configured for projecting a structure pattern onto a semiconductor substrate in an exposure unit. The exposure unit has a minimum resolution limit for projecting the structure pattern onto the semiconductor substrate. The mask has a substrate, at least one raised first structure element on the substrate which has a lateral extent which is at least the minimum lateral extent that can be attained by the exposure unit, a configuration second raised structure elements which are arranged in an area surrounding the at least one first structure element on the substrate in the form of a matrix with a row spacing and a column spacing, whose shape and size are essentially identical to one another, and which have a respective lateral extent that is less than the minimum resolution limit of the exposure unit.

Claims (40)

1. A mask for projecting a structure pattern onto a semiconductor substrate in an exposure unit, the exposure unit having a minimum resolution limit for projecting the structure pattern onto the semiconductor substrate, the mask comprising:

a substrate;

at least one raised first structure element on said substrate, said first structure element having a lateral extent amounting to at least the minimum resolution limit, said first structure element formed of a first layer and a second layer, said first layer and said second layer selected from the group consisting of opaque layers and semitransparent layers;

a configuration of raised second structure elements, said second structure elements:

being disposed in a vicinity of said first structure element on said substrate and arranged in a matrix with a row spacing and a column spacing;

being formed by only said first layer;

having a substantially identical shape and size; and

having a respective lateral extent less than the minimum resolution limit, so that the structure configuration cannot be transferred to a photosensitive resist layer formed on the semiconductor substrate.

2. The mask according to claim 1 , wherein said at least one raised first structure element is surrounded by said matrix of said second structure elements.

3. The mask according to claim 1 , wherein said at least one raised first structure element is disposed with a spacing distance from each of said raised second structure elements in said matrix.

4. The mask according to claim 1 , wherein at least one of said second structure elements formed of said first layer being an opaque layer.

5. The mask according to claim 1 , wherein at least one of said second structure elements formed of said first layer being a semitransparent layer.

6. The mask according to claim 1 , wherein:

said first structure element and said second structure elements are formed on a surface of the mask; and

said matrix of said second structure elements surrounds said first structure elements and fills up an entire area of the surface.

7. A mask blank for producing the mask according to claim 1 , comprising:

a substrate;

a first layer having a matrix configuration of structure elements on said substrate; and

a second opaque or semitransparent layer for forming first structure elements on the mask disposed above said first layer.

8. The mask blank according to claim 7 , which comprises a filling material disposed in interspaces formed in said matrix configuration.

9. The mask blank according to claim 7 , which further comprises a third semitransparent layer disposed between said first layer and said second layer.

10. The mask blank according to claim 7 , wherein said first layer with said matrix configuration of structure elements comprises molybdenum silicide.

11. The mask blank according to claim 8 , wherein said filling material in said interspaces includes at least one material selected from the group consisting of an oxide and a nitride.

12. The mask blank according to claim 8 , wherein said filling material and a material in said first layer have similar optical properties.

13. The mask blank according to claim 12 , wherein the similar optical properties include transparency and phase shift properties.

14. A method of producing a mask, which comprises:

providing a mask blank with:

a substrate;

a first layer having a matrix configuration of structure elements on the substrate; and

a second opaque or semitransparent layer for forming first structure elements on the mask disposed above said first layer;

and producing the mask according to claim 1 from the mask blank.

15. A method of producing a mask for projecting a structure pattern onto a semiconductor substrate in an exposure unit, the exposure unit having a minimum resolution limit for projecting the structure pattern onto the semiconductor substrate, the method which comprises:

providing a mask blank according to claim 7 ; and

processing the mask blank to produce a mask having:

the substrate;

at least one raised first structure element on the substrate, the first structure element having a lateral extent amounting to at least the minimum resolution limit;

a configuration of raised second structure elements, the second structure elements:

being disposed in a vicinity of the first structure element on the substrate and arranged in a matrix with a row spacing and a column spacing;

having a substantially identical shape and size; and

having a respective lateral extent less than the minimum resolution limit, so that the structure configuration cannot be transferred to a photosensitive resist layer formed on the semiconductor substrate.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT 7105729 PREVIOUSLY RECORDED AT REEL: 036827 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 26, 2017
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 043336/0694 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036827/0885 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023796/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2006
From: BUTT, SHAHID; HAFFNER, HENNING
To: INFINEON TECHNOLOGIES AG
Reel/Frame 017264/0588 →