Non-volatile flash semiconductor memory and fabrication method
View Patent ↗In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor material. The material of the gate electrodes is also present on two side walls of the fins, in order to form side wall transistors, and between the gate electrodes forms parts of a word line belonging to the corresponding fin.
1. A semiconductor memory having a row and column arrangement of bit lines and word lines with a memory cell arranged at each crossing point of a bit line and a word line, comprising:
conductively doped source/drain regions formed in fins of semiconductor material which are arranged parallel to one another, wherein the bit lines are connected to the source-drain regions;
channel regions arranged between the respective source/drain regions and located a distance from one another in a direction of the word lines;
gate electrodes, which are arranged on top and side walls of the respective fins, electrically insulated from and drive the respective channel regions, connected to the word lines, and electrically conductively connected to one another; and
storage layers, which are located between the gate electrodes and the semiconductor material on top sides of the respective fins, and are used to program the respective memory cells,
wherein the word lines are formed by parts applied to the side walls of the fins of the gate electrodes.
2. The semiconductor memory as claimed in claim 1 , wherein the memory layer is an oxide nitride oxide layer sequence.
3. The semiconductor memory as claimed in claim 1 , wherein the storage layer is a floating gate electrode, which is electrically insulated all around by the gate electrode and the semiconductor material of the fin.
4. The semiconductor memory as claimed in claim 1 , wherein the fins are formed as strip-like parts of a body silicon layer of an SOI substrate.
5. The semiconductor memory as claimed in claim 2 , wherein the fins are formed as strip-like parts of a body silicon layer of an SOI substrate.
6. The semiconductor memory as claimed in claim 3 , wherein the fins are formed as strip-like parts of a body silicon layer of an SOI substrate.
7. A semiconductor memory having a row and column arrangement of bit lines and word lines, in which a memory cell is arranged at each crossing point of a bit line and a word line, comprising:
source/drain regions formed in fins of semiconductor material which are arranged parallel to and at a distance from one another;
a storage layer arranged on a top side of each of the fins; and
a gate electrode arranged on the top side and side walls of each of the fins, the gate electrodes being electrically conductively connected to one another,
wherein the word lines are formed by parts applied to the side walls of the fins of the material of the gate electrodes.