Integrated circuit

1. An integrated circuit with a multiphase operation, comprising:

a plurality of transistors, all of the transistors being of the same type;

at least two timer signal inputs including a first timer signal input and a second timer signal input; and

a capacitor configured as a signal buffer store for momentarily storing an internal signal of the integrated circuit at least for a storage duration between a timer signal pulse at the first timer signal input and a timer signal pulse at the second timer signal input that does temporally not overlap with the pulse at the first timer signal input,

wherein the integrated circuit is produced from non-monocrystalline semiconductors.

2. The integrated circuit as claimed in claim 1 , further comprising at least one supply voltage terminal for receiving a supply voltage and at least one signal output for outputting an output signal, wherein the magnitude of the supply voltage is essentially equal to the voltage required for the output signal.

3. The integrated circuit as claimed in claim 1 , wherein all of the transistors are p-channel transistors.

4. The integrated circuit as claimed in claim 1 , further comprising at least one capacitor for buffer-storing signals.

5. The integrated circuit as claimed in claim 1 , wherein the semiconductors are organic semiconductors.

6. The integrated circuit as claimed in claim 5 , wherein the organic semiconductors are molecular semiconductors.

7. The integrated circuit as claimed in claim 5 , wherein the organic semiconductors are polymer semiconductors.

8. The integrated circuit as claimed in claim 2 , wherein the non-monocrystalline semiconductors are inorganic semiconductors, which are surface-functionalized.

9. The integrated circuit as claimed in claim 8 , wherein the semiconductors are surface-functionalized nanoparticles of inorganic nature.

10. The integrated circuit as claimed in claim 2 , which forms a NOR gate.

11. The integrated circuit as claimed in claim 10 , comprising:

first to fourth transistors, each having a gate terminal, a source terminal and a drain terminal;

first and second capacitors;

a resistor;

first and second timer signal inputs; and

first and second signal inputs,

wherein

the gate terminal of the first transistor is signal-connected to the first timer signal input via the first capacitor and to the supply voltage terminal via the resistor,

the source terminal of the first transistor is signal-connected to the supply voltage terminal,

the drain terminal of the first transistor, the source terminal of the third transistor, the source terminal of the fourth transistor and the signal output are signal-connected to one another,

the drain terminal of the first transistor is grounded via the second capacitor,

the first signal input is signal-connected to the gate terminal of the third transistor,

the second signal input is signal-connected to the gate terminal of the fourth transistor,

the drain terminal of the third transistor, the drain terminal of the fourth transistor and the source terminal of the second transistor are signal-connected to one another,

the gate terminal of the second transistor is signal-connected to the second timer signal input, and

the drain terminal of the second transistor is grounded.

12. The integrated circuit as claimed in claim 1 , which forms a phase shifter.

13. The integrated circuit as claimed in claim 12 , comprising:

first to sixth p-channel transistors;

first to fourth capacitors;

first and second timer signal inputs;

a signal input; and

a signal output,

wherein

the first timer signal input is signal connected to the gate terminal of the first transistor and the gate terminal of the second transistor,

the source terminal of the first transistor is connected to the supply voltage,

the drain terminal of the first transistor is signal connected to an intermediate signal output and the source terminal of the third transistor,

the source terminal of the second transistor is signal connected to the signal input,

the drain terminal of the second transistor is signal connected to the gate terminal of the third transistor and the first terminal of the first capacitor,

the second timer signal input is signal connected to the gate terminal of the fourth transistor and the gate terminal of the fifth transistor,

the source terminal of the fourth transistor is connected to the supply voltage,

the drain terminal of the fourth transistor is signal connected to the signal output, the source terminal of the sixth transistor and the first terminal of the fourth capacitor,

the source terminal of the fifth transistor is signal connected to the intermediate signal output and the first terminal of the second capacitor,

the drain terminal of the fifth transistor is signal connected to the gate terminal of the sixth transistor the first terminal of the third capacitor, and

the second terminal of the first capacitor, the drain terminal of the third transistor, the second terminal of the fourth capacitor, the second terminal of the second capacitor, the second terminal of the third capacitor and the drain terminal of the sixth transistor are each grounded.