IP Library Granted Patent US 6,999,355
Granted Patent B2
US 6,999,355 · App. 10/841,546 · Granted Feb 14, 2006

Circuit arrangement and method for setting a voltage supply for a read/write amplifier of an integrated memory

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Quick Facts
Patent No.
US 6,999,355
App. No.
10/841,546
Granted
Feb 14, 2006
Kind
B2
Abstract

A circuit arrangement for setting a voltage supply for a read/write amplifier of an integrated memory has a first voltage generator circuit for generating a supply voltage for application to the read/write amplifier during an assessment and amplification operation and a second voltage generator circuit for generating a precharge voltage for precharging bit lines of the memory which are connected to the read/write amplifier. A temperature detector circuit, which is connected to the first voltage generator circuit, is used to detect a temperature of the memory and interacts with the first voltage generator circuit to set the supply voltage applied to the read/write amplifier in a manner depending on a temperature of the memory.

Claims (10)

1. A circuit arrangement for setting a voltage supply for a read/write amplifier of an integrated memory for assessing and amplifying signals stored in memory cells comprising:

a first voltage generator circuit that generates a supply voltage for application to the read/write amplifier during an assessment and amplification operation, wherein the first voltage generator circuit generates the supply voltage for application to the read/write amplifier depending on a temperature of the memory such that a change in the supply voltage behaves proportionally to a temperature-dictated change in a transistor threshold voltage of a transistor used in the read/write amplifier and such that a difference between a precharge voltage and the transistor threshold voltage is constant;

a second voltage generator circuit that generates a precharge voltage for precharging bit lines of the memory which are connected to the read/write amplifier, the second voltage generator circuit regulating the precharge voltage to a bias value which behaves proportionally to the supply voltage applied to the read/write amplifier; and

a temperature detector circuit for detecting a temperature of the memory, the temperature detector circuit being connected to the first voltage generator circuit and interacting with the first voltage generator circuit to set the supply voltage applied to the read/write amplifier depending on a temperature of the memory.

2. The circuit arrangement as claimed in claim 1 , wherein the second voltage generator circuit regulates the precharge voltage to a bias value, a magnitude of the bias value being half the magnitude of the supply voltage applied to the read/write amplifier.

3. A method for setting a voltage supply for a read/write amplifier of an integrated memory for assessing and amplifying signals stored in memory cells, comprising:

detecting a temperature change of the integrated memory;

generating and setting of a supply voltage for application to the read/write amplifier during an assessment and amplification operation depending on a temperature change in such a way that a change in the supply voltage behaves proportionally to a temperature-dictated change in a transistor threshold voltage of a transistor used in the read/write amplifier and such that a difference between the precharge voltage and the transistor threshold voltage is constant; and

generating and setting of a precharge voltage for precharging bit lines of the memory proportionally to the supply voltage applied to the read/write amplifier the bit lines being connected to the read/write amplifier.

4. The method as claimed in claim 3 , wherein, as the temperature of the memory falls, a magnitude of the supply voltage for application to the read/write amplifier is raised.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036873/0758 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023821/0535 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2004
From: BENZINGER, HERBERT; VAN DER ZANDEN, KOEN; SCHRODER, STEPHEN; PROLL, MANFRED
To: INFINEON TECHNOLOGIES AG
Reel/Frame 015578/0010 →