Memory data bus structure and method of transferring information with plural memory banks
View Patent ↗A data bus structure for a dynamic random access memory (DRAM) according to the present invention includes a series of data buses, each shared by a plurality of memory banks, and a switching device to selectively couple the data buses to a global data bus to enable the memory device to provide and receive data. The data bus structure conserves space on a chip or die and prevents significant timing skews for data accessed from different memory banks.
1. An apparatus for transporting data within a memory device including a plurality of memory banks and a series of pads receiving information for and providing information from said memory device, said apparatus comprising:
a plurality of bank data buses each associated with at least two of said memory banks to transfer information with those memory banks;
a global data bus to transfer information with said series of pads to receive information for and provide information from said memory device; and
a switching device coupled to said plurality of bank data buses and to said global data bus to selectively couple one of said bank data buses to said global data bus in accordance with a desired memory bank to access in order to transfer information between said series of pads and said desired memory bank.
2. The apparatus of claim 1 , wherein said switching device includes a multiplexer.
3. The apparatus of claim 1 , wherein said memory device includes eight memory banks.
4. The apparatus of claim 3 , wherein said apparatus includes four bank data buses, with each bank data bus associated with two memory banks, and wherein said switching device selectively couples one of said four bank data buses to said global data bus.
5. The apparatus of claim 1 , wherein said memory device includes a dynamic random access memory.
6. A method of transporting data within a memory device including a plurality of memory banks and a series of pads receiving information for and providing information from said memory device, said method comprising:
(a) associating each of a plurality of bank data buses with at least two of said memory banks to transfer information with those memory banks; and
(b) transferring information between said series of pads and a desired memory bank by selectively coupling, via a switching device, said bank data bus associated with said desired memory bank to a global data bus that transfers information with said series of pads to receive information for and provide information from said memory device.
7. The method of claim 6 , wherein said switching device includes a multiplexer, and step (b) further includes:
(b.1) selectively coupling, via said multiplexer, said bank data bus associated with said desired memory bank to said global data bus.
8. The method of claim 6 , wherein said memory device includes eight memory banks.
9. The method of claim 8 , wherein said plurality of bank data buses includes four bank data buses, and step (a) further includes:
(a.1) associating each of said four bank data buses with two of said memory banks to transfer information with those memory banks.
10. The method of claim 6 , wherein said memory device includes a dynamic random access memory.
11. An apparatus for transporting data within a memory device including a plurality of memory banks and a series of pads receiving information for and providing information from said memory device, said apparatus comprising:
a plurality of transport means each associated with at least two of said memory banks for transferring information with those memory banks;
global transport means for transferring information with said series of pads to receive information for and provide information from said memory device; and
switching means coupled to said plurality of transport means and to said global transport means to selectively couple one of said transport means to said global transport means in accordance with a desired memory bank to access in order to transfer information between said series of pads and said desired memory bank.
12. The apparatus of claim 11 , wherein said switching means includes a multiplexer.
13. The apparatus of claim 11 , wherein said memory device includes eight memory banks.
14. The apparatus of claim 13 , wherein said apparatus includes four transport means, with each transport means associated with two memory banks, and wherein said switching means selectively couples one of said four transport means to said global transport means.
15. The apparatus of claim 1 , wherein said memory device includes a dynamic random access memory.
16. A memory device comprising:
a plurality of memory banks;
a series of pads receiving information for and providing information from said memory device;
a plurality of bank data buses each associated with at least two of said memory banks to transfer information with those memory banks;
a global data bus to transfer information with said series of pads to receive information for and provide information from said memory device; and
a switching device coupled to said plurality of bank data buses and to said global data bus to selectively couple one of said bank data buses to said global data bus in accordance with a desired memory bank to access in order to transfer information between said series of pads and said desired memory bank.
17. The memory device of claim 16 , wherein said switching device includes a multiplexer.
18. The memory device of claim 16 , wherein said memory device includes eight memory banks.
19. The memory device of claim 18 , wherein said memory device includes four bank data buses, with each bank data bus associated with two memory banks, and wherein said switching device selectively couples one of said four bank data buses to said global data bus.
20. The memory device of claim 16 , wherein said memory device includes a dynamic random access memory.