Integrated circuit including a memory fabricated using self-aligned processing
View Patent ↗An integrated circuit includes transistors in rows and columns providing an array, conductive lines in columns across the array, and resistivity changing material elements contacting the conductive lines and self-aligned to the conductive lines. The integrated circuit includes electrodes contacting the resistivity changing material elements, each electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.
1. A method for fabricating an integrated circuit including a memory, the method comprising:
providing a preprocessed wafer including first contacts;
depositing a first electrode material layer over the preprocessed wafer;
depositing a first phase change material layer over the first electrode material layer;
etching the first phase change material layer and the first electrode material layer self-aligned to the first phase change material layer to form lines of first phase change material and first electrode material contacting the first contacts;
depositing a dielectric material layer over exposed portions of the first phase change material, the first electrode material, and the preprocessed wafer;
planarizing the dielectric material layer to expose the first phase change material;
depositing a second phase change material layer over the first phase change material and the dielectric material layer;
depositing a second electrode material layer over the second phase change material layer; and
etching the second electrode material layer, the second phase change material layer, the first phase change material, and the first electrode material to form conductive lines, phase change material self-aligned to the conductive lines providing storage locations, and bottom electrodes self-aligned to the conductive lines and contacting the first contacts.
2. The method of claim 1 , further comprising:
depositing a hardmask material layer over the first phase change material layer; and
etching the hardmask material layer, the first phase change material layer self-aligned to the hardmask material layer, and the first electrode material layer self-aligned to the hardmask material layer to form lines of hardmask material, first phase change material, and first electrode material.
3. The method of claim 1 , wherein providing the preprocessed wafer comprises providing a preprocessed wafer including transistors, second contacts, and ground lines, a source-drain path of each transistor coupled between a first contact and a second contact, each second contact coupled to a ground line.
4. A method for fabricating an integrated circuit including a memory, the method comprising:
providing a preprocessed wafer including first contacts;
depositing a first electrode material layer over the preprocessed wafer;
depositing a hardmask material layer over the first electrode material layer;
etching the hardmask material layer and the first electrode material layer self-aligned to the hardmask material layer to form lines of hardmask material and first electrode material contacting the first contacts;
depositing a dielectric material layer over exposed portions of the of hardmask material, the first electrode material, and the preprocessed wafer;
planarizing the dielectric material layer to expose the hardmask material;
removing the hardmask material;
depositing a phase change material layer over the dielectric material layer and the first electrode material;
depositing a second electrode material layer over the phase change material layer; and
etching the second electrode material layer, the phase change material layer, and the first electrode material to form conductive lines, phase change material self-aligned to the conductive lines providing storage locations, and bottom electrodes self-aligned to the conductive lines and contacting the first contacts.
5. The method of claim 4 , wherein providing the preprocessed wafer comprises providing a preprocessed wafer including transistors, second contacts, and ground lines, a source-drain path of each transistor coupled between a first contact and a second contact, each second contact coupled to a ground line.
6. A method for fabricating an integrated circuit including a memory, the method comprising:
providing a preprocessed wafer including first contacts;
depositing a first electrode material layer over the preprocessed wafer;
depositing a phase change material layer over the first electrode material layer;
etching the phase change material layer and the first electrode material layer self-aligned to the phase change material layer to form lines of phase change material and first electrode material contacting the first contacts;
depositing a dielectric material layer over exposed portions of the phase change material, the first electrode material, and the preprocessed wafer;
planarizing the dielectric material layer to expose the phase change material;
depositing a second electrode material layer over the phase change material and the dielectric material layer; and
etching the second electrode material layer, the phase change material, and the first electrode material to form conductive lines, phase change elements self-aligned to the conductive lines, and bottom electrodes self-aligned to the conductive lines and contacting the first contacts.
7. The method of claim 6 , further comprising:
depositing a hardmask material layer over the phase change material layer; and
etching the hardmask material layer, the phase change material layer self-aligned to the hardmask material layer, and the first electrode material layer self-aligned to the hardmask material layer to form lines of hardmask material, phase change material, and first electrode material.
8. The method of claim 6 , wherein providing the preprocessed wafer comprises providing a preprocessed wafer including transistors, second contacts, and ground lines, a source-drain path of each transistor coupled between a first contact and a second contact, each second contact coupled to a ground line.
9. A method for fabricating an integrated circuit including a memory, the method comprising:
providing a preprocessed wafer including first contacts;
depositing a first electrode material layer over the preprocessed wafer;
depositing a phase change material layer over the first electrode material layer;
depositing a second electrode material layer over the phase change material layer;
etching the second electrode material layer, the phase change material layer self-aligned to the second electrode material layer, and the first electrode material layer self-aligned to the second electrode material layer to form lines of second electrode material, phase change material, and first electrode material contacting the first contacts;
depositing a dielectric material layer over exposed portions of the second electrode material, the phase change material, the first electrode material, and the preprocessed wafer;
planarizing the dielectric material layer to expose the second electrode material;
depositing a third electrode material layer over the second electrode material and the dielectric material layer; and
etching the third electrode material layer, the second electrode material, the phase change material, and the first electrode material to form conductive lines, top electrodes self-aligned to the conductive lines, phase change elements self-aligned to the conductive lines, and bottom electrodes self-aligned to the conductive lines and contacting the first contacts.
10. The method of claim 9 , further comprising:
depositing a hardmask material layer over the second electrode material layer; and
etching the hardmask material layer, the second electrode material layer self-aligned to the hardmask material layer, the phase change material layer self-aligned to the hardmask material layer, and the first electrode material layer self-aligned to the hardmask material layer to form the lines of second electrode material, phase change material, and first electrode material.
11. The method of claim 9 , wherein providing the preprocessed wafer comprises providing a preprocessed wafer including transistors, second contacts, and ground lines, a source-drain path of each transistor coupled between a first contact and a second contact, each second contact coupled to a ground line.