Integrated circuit including a memory module having a plurality of memory banks
View Patent ↗An integrated circuit including a memory module having a plurality of memory banks is disclosed. One embodiment provides an even number of at least four memory banks. Each memory bank has a plurality of memory cells. Each two of the memory bank form a memory bank region and being alternately connected to an m-bit data bus. The memory banks are classified into two groups, each group including a memory bank of each memory bank region. The memory module further includes a selection device connected to the memory banks and being responsive to selection bits. The selection device selects one of the two groups of memory banks and a group of i memory cells within the memory banks of the selected group of memory banks to access the selected i memory cells per one stroke via the associated m-bit data buses of the memory groups including the selected memory banks, m being equal to an integer multiple of i.
1. An integrated circuit including a memory module comprising:
an even number of at least four memory banks, each memory bank having a plurality of memory cells, each memory bank comprising a column path region, each two memory banks forming a memory bank region and having a common data port, the column path region of each of the two memory banks including a data in/out connection to the common data port, the two memory banks of the memory bank region being alternately connected to a m-bit data bus via the common data port, each memory bank being subdivided into memory bank segments, each two memory bank segments forming a memory bank group and sharing a common data bus in the column path region to the common data port, the memory banks being classified into two groups, each group comprising a memory bank of each memory bank region; and
a selection device, the selection device selecting one of the two groups of memory banks, and a group of i memory cells within one of the two memory bank segments of memory bank groups of the memory banks of the selected group of memory banks to access the selected i memory cells per one stroke via the associated m-bit data buses of the memory groups, m being equal to an integer multiple of i, and i and m being positive integers.
2. The integrated circuit of claim 1 , further comprising a central data register connected between the respective m-bit data bus of each memory group and an n-bit data port, n being a positive integer.
3. The integrated circuit of claim 2 , wherein n is equal to an integer multiple of m, the central data register buffering and transmitting an n-bit data packet between the n-bit data port and the m-bit data buses of the memory groups.
4. The integrated circuit of claim 1 , wherein the selection device is responsive to selection bits and being operated in one of an m-bit mode and a m/2-bit mode to access the memory bank regions.
5. The integrated circuit of claim 1 , wherein m is equal to 8.
6. The integrated circuit of claim 1 , comprising:
where the memory module comprises a donut architecture.
7. A memory module comprising:
an even number of at least four memory banks, each memory bank having a plurality of memory cells, each memory bank comprising a column path region, each two of the memory banks forming a memory bank region and having a common data port, the column path region of each of the two memory banks including a data in/out connection to the common data port, the two memory banks of the memory bank region being alternately connected to a m-bit data bus via the common data port, each memory bank being subdivided into memory bank segments, each two memory bank segments forming a memory bank group and sharing a common data bus in the column path region to the common data port, the memory banks being classified into two groups, each group comprising a memory bank of each memory bank region; and
a selection device connected to the memory banks and being responsive to selection bits, the selection device selecting one of the two groups of memory banks and a group of i memory cells within one of the two memory bank segments of memory bank groups of the memory banks of the selected group of memory banks to access the selected i memory cells per one stroke via the associated m-bit data buses of the memory groups including the selected memory banks, m being equal to an integer multiple of i, and i and m being positive integers.
8. The memory module of claim 7 , further comprising a central data register connected between the respective m-bit data bus of each memory group and an n-bit data port, n being equal to an integer multiple of m, the central data register buffering and transmitting an n-bit data packet between the n-bit data port and the m-bit data buses of the memory groups, n being a positive integer.