IP Library Granted Patent US 7,662,721
Granted Patent B2
US 7,662,721 · App. 11/376,645 · Granted Feb 16, 2010

Hard mask layer stack and a method of patterning

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Quick Facts
Patent No.
US 7,662,721
App. No.
11/376,645
Granted
Feb 16, 2010
Kind
B2
Abstract

A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO 2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Claims (30)

1. A method of patterning a layer to be patterned, comprising:

providing a layer to be patterned;

providing a hard mask layer stack, comprising a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from a group comprising of SiO 2 and SiON disposed on top of the carbon layer, and a silicon layer disposed on top of the first layer, on the layer to be patterned;

providing, a first photoresist layer on top of the silicon layer;

imaging first structures in a first exposure using a first photomask into the first photoresist layer; and

developing the first photoresist layer, so as to generate a photoresist pattern on the silicon layer;

etching the portions of the silicon layer uncovered by the fist photoresist pattern thereby forming first patterns;

removing the first photoresist layer from the silicon layer leaving a surface of a substrate with regions covered by the silicon layer and regions with uncovered first layer of the hard mask layer stack;

providing a second photoresist layer on top of the surface of the substrate;

imaging second structures in a second exposure using a second photomask into the second photoresist layer;

developing the second photoresist, so as to generate a photoresist pattern on the surface of the substrate; and

etching the uncovered portions of the silicon layer uncovered by the second photoresist pattern thereby forming second patterns;

patterning the first layer and the carbon layer in accordance with the second patterns; and

etching the uncovered portions of the layer to be patterned.

2. The method of claim 1 , wherein the first structures comprise conductive lines and the second structures comprise landing pads connected with the conductive lines of a semiconductor device.

3. A method of patterning comprising:

providing a hard mask layer stack on a layer to be patterned;

wherein the hard mask layer stack comprises a carbon layer, a first layer of a material selected from a group comprising of SiO 2 and SiON, and a silicon layer;

providing a first photoresist layer on top of the silicon layer;

imaging first structures in a first exposure using a first photomask into the first photoresist layer;

developing the first photoresist layer, so as to generate a first photoresist pattern on the silicon layer;

etching the portions of the silicon layer uncovered by the first photoresist pattern thereby forming first patterns;

removing the first photoresist layer from the silicon layer leaving a surface of a substrate with regions covered by the silicon layer and regions with uncovered first layer of the hard mask layer stack;

providing a second photoresist layer on top of the surface of the substrate;

imaging second structures in a second exposure using a second photomask into the second photoresist layer:

developing the second photoresist, so as to generate a second photoresist pattern on the surface of the substrate;

etching the portions of the silicon layer uncovered by the second photoresist pattern thereby forming second patterns;

patterning the first layer and the carbon layer in accordance with the second patterns; and

etching the uncovered portions of the layer to be patterned.

4. The method of claim 3 , wherein the first structures comprise conductive lines and the second structures comprise landing pads connected with the conductive lines of a semiconductor device.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2017
From: GUTKIN, LARISSA, SUCCESSOR MICHAEL GUTKIN; GUTKIN, MICHAEL
To: GUTKIN, LARISSA
Reel/Frame 045506/0220 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037171/0719 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037147/0487 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2006
From: MANGER, DIRK; BOUBEKEUR, HOCINE; VERHOEVEN, MARTIN; NAGEL, NICOLAS; TATRY, THOMAS; CASPARY, DIRK; MARKERT, MATTHIAS
To: INFINEON TECHNOLOGIES AG
Reel/Frame 018214/0706 →