Reducing leakage current in memory device using bitline isolation
View Patent ↗A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof. At least one bank-specific isolation control signal is independently generated for each of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in a memory bank. The at least one bank-specific isolation control signal is supplied to at least one sense amplifier column in the corresponding memory bank to isolate at least one side to at least one memory array that is in an unselected state in a corresponding memory bank.
1. A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof, the method comprising:
a. independently generating first and second bank-specific isolation control signals for each of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in a memory bank; and
b. supplying the first and second bank-specific isolation control signals to sense amplifier columns in corresponding memory banks such that the same side of all the sense amplifier columns in a memory bank is isolated from a memory array when in an unselected state.
2. The method of claim 1 , wherein supplying comprises supplying the first and second bank-specific isolation control signals to the sense amplifier columns in the corresponding memory banks such that both sides of all the sense amplifier columns in a memory bank are isolated from memory arrays.
3. The method of claim 1 , and further comprising storing information identifying locations in a memory bank having an anomalous bitline leakage for each of the memory banks.
4. The method of claim 3 , wherein storing comprises blowing one or more fuses associated with each of the plurality of memory banks to represent information locations in a memory bank having an anomalous bitline leakage for each of the memory banks, and wherein said independently generating is based on states of fuses for the corresponding memory bank.
5. The method of claim 3 , wherein said independently generating comprises generating the first and second bank-specific isolation control signals based on stored information identifying locations in a memory bank having an anomalous bitline leakage for each of the memory banks.
6. A semiconductor memory device comprising:
a. a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof; and
b. bank-specific control logic associated with each of the memory banks, wherein each bank-specific control logic generates first and second bank- specific isolation control signals for a corresponding one of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in the memory bank, wherein said first and second bank-specific isolation control signals are routed to sense amplifier columns in the corresponding memory bank such that the same side of all the sense amplifier columns in the memory bank is isolated from a memory array when in an unselected state.
7. The memory device of claim 6 , and further comprising a plurality of fuses associated with each of the memory banks, wherein one or more of the plurality of fuses is blown to identify locations in a memory bank having an anomalous bitline leakage for each of the memory banks, and wherein the bank-specific control logic generates the first and second bank-specific isolation control signals based on states of said plurality of fuses for the corresponding memory bank.
8. The memory device of claim 6 , wherein said bank-specific control logic generates the first and second bank-specific isolation control signals based on stored information identifying locations in a memory bank having an anomalous bitline leakage for each of the memory banks.
9. The memory device of claim 6 , wherein said first and second bank-specific isolation control signals are routed to the sense amplifier columns in the corresponding memory banks such that both sides of all the sense amplifier columns are isolated from memory arrays.
10. A semiconductor memory device comprising:
a. means for storing data in a plurality of memory arrays comprised of storage cells;
b. a plurality of means for sensing interspersed between memory arrays such that a means for sensing is shared by the memory arrays on opposite sides thereof; and
c. means for generating first and second control signals that is are connected to the plurality of means for sensing such that the same side of all of the means for sensing is isolated from a memory array in corresponding memory bank when in an unselected state depending on existence and location of an anomalous bitline leakage in the memory bank.
11. The memory device of claim 10 , wherein said means for generating generates the first and second control signals based on stored information identifying locations having the anomalous bitline leakage for the memory bank.