A device or method for activating a memory, which includes receiving a select signal at the memory, receiving a plurality of address bits at the memory, determining whether the select signal is active, determining whether a first bit in the plurality of address bits has a first value, and activating the memory only if the select is active and the first bit has the first value.
1. A semiconductor memory device, comprising:
a first memory configured to store a first plurality of data bits;
a second memory configured to store a second plurality of data bits; and
a memory controller configured to receive a select signal and a plurality of address bits, and to control operation of the first and second memories,
wherein the memory controller activates the first memory only when the select signal is active and when an activation bit selected from the plurality of address bits has a first value, and activates the second memory only when the select signal is active and when the activation bit has a second value.
2. The semiconductor memory of claim 1 , further comprising:
a third memory configured to store a third plurality of data bits,
wherein the memory controller circuit activates the first memory only when the select signal is active, when the activation bit has the first value, and when an address selected from the plurality of address bits matches a first identifier, and activates the third memory only when the select signal is active, when the activation bit has the first value, and when the address matches a third identifier.
3. The semiconductor memory of claim 1 , wherein the memory controller comprises:
a first memory control circuit configured to receive the select signal and the plurality of address bits, and to control operation of the first memory; and
a second memory control circuit configured to receive the select signal and the plurality of address bits, and to control operation of the second memory,
wherein the first memory control circuit activates the first memory only when the select signal is active and when the activation bit has a first value, and
wherein the second memory control circuit activates the second memory only when the select signal is active and when the activation bit has a second value.
4. The semiconductor memory of claim 1 , wherein the activation bit is received at the memory controller at the same time as the address is received.
5. The semiconductor memory of claim 1 , wherein the activation bit is received at the memory controller at the same time as one of a row address or a column address selected from the plurality of address bits is received.
6. The semiconductor memory of claim 1 , wherein the first value corresponds to an active voltage and the second value corresponds to an inactive voltage.
7. A method of operating a semiconductor memory, comprising:
receiving a select signal at a first memory; and a second memory;
receiving an address bit at the first memory; and at the second memory;
determining whether the select signal is active;
determining whether the address bit has a first value or a second value; and
accessing the first memory only when the select signal is active and the address bit has the first value, and the second memory only when the select signal is active and the address bit has the second value.
8. The method of claim 7 , wherein the address bit is one of a bank address bit and a row address bit.
9. The method of claim 7 , wherein the accessing of the first memory comprises one of reading data from the first memory or writing data to the first memory.
10. The method of claim 7 , wherein the first value is one of a positive reference voltage and a ground voltage.
11. A memory activation circuit, comprising:
a comparison circuit configured to receive a reference voltage and an activation identifier bit, and to output a first intermediate signal indicating whether a value of the activation identifier bit is equal to the reference voltage;
a decoder configured to receive an address, and to output a second intermediate signal indicating whether the address matches an identifier; and
a memory activation circuit configured to receive the first and second intermediate signals and to generate an activation signal, the activation signal indicating that the memory should be activated only when the first intermediate signal indicates that the value of the activation identifier bit is equal to the reference voltage and the second intermediate signal indicates that the address matches the identifier.
12. The memory activation circuit of claim 11 , wherein the comparison circuit comprises an exclusive OR gate.
13. The memory activation circuit of claim 11 , wherein the memory activation circuit comprises:
an AND gate configured to receive the first and second intermediate signals and to generate a third intermediate signal; and
a flip-flop configured to receive the third intermediate signal and to generate the activation signal.
14. The memory activation circuit of claim 11 , wherein the activation bit is received at the comparison circuit at the same time as the address is received at the decoder.
15. The memory activation circuit of claim 11 , wherein the activation bit is received at the comparison circuit at the same time as one of a row address or a column address selected from the plurality of address bits is received at the memory activation circuit.
16. A memory activation circuit, comprising:
means for comparing a reference voltage and an activation identifier bit, and outputting a first intermediate signal indicating whether a value of the activation identifier bit is equal to the reference voltage;
means for decoding an address and outputting a second intermediate signal indicating whether the address matches an identifier; and
means for generating an activation signal, the activation signal indicating that the memory should be activated only when the first intermediate signal indicates that the value of the activation identifier bit is equal to the reference voltage and the second intermediate signal indicates that the address matches the identifier.
17. The memory activation circuit of claim 16 , wherein the means for comparing comprises a means for performing an exclusive OR operation.
18. The memory activation circuit of claim 16 , wherein the means for generating an activation signal comprises:
means for performing an AND operation on the first and second intermediate signals, and to generate a third intermediate signal; and
means for generating the activation signal based on the third intermediate signal.
19. The memory activation circuit of claim 16 , wherein the activation bit is received at the means for comparing at the same time as the address is received at the means for decoding.
20. The memory activation circuit of claim 16 , wherein the activation bit is received at the means for comparing at the same time as one of a row address or a column address selected from the plurality of address bits is received at the means for generating a k activation signal.
21. A method of activating one of at least two memory banks in a memory chip, including:
receiving a chip select signal at the memory chip;
receiving a plurality of address bits at the memory chip;
determining whether the chip select signal is active;
determining whether a first bit in the plurality of address bits has a first value or a second value; and
activating a first memory bank only if the chip select is active and the first bit has the first value, and a second memory bank only if the chip select is active and the first bit has the second value.
22. The method of claim 21 , further comprising:
determining whether a bit sequence selected from the plurality of address bits matches a bank identifier,
wherein the activating of the memory bank occurs only if the bit sequence matches the bank identifier.
23. The method of claim 21 , wherein the first value is one of an active voltage and an inactive voltage.
24. The method of claim 23 , wherein the active voltage is a positive reference voltage, and the inactive voltage is a ground voltage.