Method of manufacturing a transistor and memory cell array
View Patent ↗A transistor of an integrated circuit includes a first and second source/drain regions, a channel region connecting the first and second source/drain regions, and a gate electrode configured to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, that is defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d 1 , wherein the depth d 1 is measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate in a distance to the top surface that is less than the depth d 1.
1. A method of fabricating an integrated circuit including a transistor, the method comprising:
forming a gate groove extending in a surface of a semiconductor substrate;
forming a first source/drain region and a second source/drain region in the semiconductor substrate, wherein the first and second source/drain regions are adjacent the substrate surface and extend to a first depth as measured from the substrate surface;
forming a spacer on a sidewall of the gate groove, wherein the spacer extends from the substrate surface to a depth which is less than the first depth;
forming a gate electrode in the gate groove, wherein a top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate at a second depth which is less than the first depth, the second depth being measured from the substrate surface, wherein an upper groove portion is defined above the gate electrode; and
filling the upper groove portion with an insulating material, wherein the spacer is removed subsequent to forming the gate electrode and prior to filling the upper groove portion with an insulating material.
2. The method of claim 1 , wherein filling the upper groove portion with an insulating material comprises non-conformally depositing the insulating material.
3. The method of claim 1 , wherein:
forming a gate groove comprises etching a first groove in the substrate surface and vertically extending the first groove; and
the spacer is formed subsequent to etching the first groove and prior to vertically extending the first groove.
4. The method of claim 1 , wherein forming a gate groove comprises etching a first groove in the substrate surface, and vertically extending the first groove by anisotropic etching of the semiconductor substrate.
5. The method of claim 4 , wherein the spacer structure is effective as an etch mask for vertically extending the first groove.
6. The method of claim 1 , wherein the spacer extends from the substrate surface to a depth which is greater than the second depth.
7. The method of claim 1 , wherein the spacer structures are formed by thermal oxidation of the semiconductor substrate.
8. The method of claim 1 , wherein a vacuum spacer is formed in the gate groove.
9. A method of fabricating an integrated circuit including a transistor, the method comprising:
forming a gate groove extending in a surface of a semiconductor substrate, the gate groove being formed with a fin-like portion including a ridge at the bottom of the gate groove;
forming a first source/drain region and a second source/drain region in the semiconductor substrate, wherein the first and second source/drain regions are adjacent the substrate surface and extend to a first depth as measured from the substrate surface;
forming a spacer on a sidewall of the gate groove, wherein the spacer extends from the substrate surface to a depth which is less than the first depth; and
forming a gate electrode in the gate groove, wherein a top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate at a second depth which is less than the first depth, the second depth being measured from the substrate surface, wherein an upper groove portion is defined above the gate electrode.