IP Library Granted Patent US 8,017,930
Granted Patent B2
US 8,017,930 · App. 11/643,438 · Granted Sep 13, 2011

Pillar phase change memory cell

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Quick Facts
Patent No.
US 8,017,930
App. No.
11/643,438
Granted
Sep 13, 2011
Kind
B2
Abstract

A memory cell includes a first electrode, a storage location, and a second electrode. The storage location includes a phase change material and contacts the first electrode. The storage location has a first cross-sectional width. The second electrode contacts the storage location and has a second cross-sectional width greater than the first cross-sectional width. The first electrode, the storage location, and the second electrode form a pillar phase change memory cell.

Claims (52)

1. A memory cell comprising:

a first electrode;

a storage location comprising phase change material and contacting the first electrode, the storage location having a first cross-sectional width;

a second electrode having a surface contacting the storage location, the second electrode having a second cross-sectional width greater than the first cross-sectional width;

an insulation material laterally surrounding a first portion of the second electrode; and

an etch stop material layer laterally surrounding a second portion of the second electrode and not directly contacting the storage location, the etch stop material different than the insulation material and the etch stop material layer having a surface coplanar with the surface of the second electrode,

wherein the first electrode, the storage location, and the second electrode form a pillar phase change memory cell.

2. The memory cell of claim 1 , wherein the storage location comprises a stack of phase change material layers.

3. The memory cell of claim 2 , further comprising:

a diffusion barrier layer between adjacent phase change material layers.

4. The memory cell of claim 1 , wherein the phase change material comprises at least one of Ge, Sb, Te, Ga, As, In, Se, and S.

5. The memory cell of claim 1 , further comprising:

a dielectric material laterally surrounding the storage location, the dielectric material different than the insulation material and the etch stop material.

6. The memory cell of claim 1 , further comprising:

a diffusion barrier layer between the storage location and the first electrode.

7. The memory cell of claim 1 , further comprising:

a diffusion barrier layer between the storage location and the second electrode.

8. The memory cell of claim 1 , wherein the storage location has a sublithographic cross-sectional width.

9. A memory cell comprising:

a first electrode;

a storage location comprising a stack of at least two planar phase change material layers, at least two of the phase change material layers in the stack comprising different phase change materials, the storage location coupled to the first electrode and having a first cross-sectional width;

a second electrode coupled to the storage location, the second electrode having a second cross-sectional width greater than the first cross-sectional width;

an insulation material laterally surrounding a first portion of the second electrode; and

an etch stop material layer laterally surrounding a second portion of the second electrode, the etch stop material different than the insulation material;

wherein the first electrode, the storage location, and the second electrode form a pillar phase change memory cell, and

wherein a bottom surface of the etch stop material layer is coplanar with a bottom surface of the second electrode.

10. The memory cell of claim 9 , wherein the storage location comprises three phase change material layers and adjacent phase change material layers comprises different phase change materials.

11. The memory cell of claim 9 , wherein the phase change materials comprises at least one of Ge, Sb, Te, Ga, As, In, Se, and S.

12. The memory cell of claim 9 , further comprising:

an insulation material laterally surrounding the second electrode; and

dielectric material laterally surrounding the storage location, the dielectric material different than the insulation material.

13. The memory cell of claim 9 , wherein the storage location has a sublithographic cross-sectional width.

14. The memory cell of claim 9 , wherein the storage location directly contacts the first electrode.

15. The memory cell of claim 9 , wherein the storage location directly contacts the second electrode.

16. The memory cell of claim 9 , wherein the storage location directly contacts the first electrode and the second electrode.

17. A memory cell comprising:

a first electrode;

a storage location comprising a stack of at least two phase change material layers, at least two of the phase change material layers in the stack comprising different phase change materials, the storage location coupled to the first electrode and having a first cross-sectional width;

a second electrode coupled to the storage location, the second electrode having a second cross-sectional width greater than the first cross-sectional width;

an insulation material laterally surrounding a first portion of the second electrode; and

an etch stop material layer laterally surrounding a second portion of the second electrode, the etch stop material different than the insulation material;

wherein the first electrode, the storage location, and the second electrode form a pillar phase change memory cell, and

wherein a bottom surface of the etch stop material layer is coplanar with a bottom surface of the second electrode.

18. The memory cell of claim 17 , wherein the storage location comprises three phase change material layers and adjacent phase change material layers comprises different phase change materials.

19. The memory cell of claim 17 , wherein the phase change materials comprises at least one of Ge, Sb, Te, Ga, As, In, Se, and S.

20. The memory cell of claim 17 , further comprising:

an insulation material laterally surrounding the second electrode; and

dielectric material laterally surrounding the storage location, the dielectric material different than the insulation material.

21. The memory cell of claim 17 , wherein the storage location has a sublithographic cross-sectional width.

22. The memory cell of claim 17 , wherein the storage location directly contacts the first electrode.

23. The memory cell of claim 17 , wherein the storage location directly contacts the second electrode.

24. The memory cell of claim 17 , wherein the storage location directly contacts the first electrode and the second electrode.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037171/0719 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037147/0487 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2011
From: QIMONDA NORTH AMERICA CORP
To: QIMONDA AG
Reel/Frame 026138/0613 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2007
From: PHILIPP, JAN BORIS; HAPP, THOMAS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018869/0747 →