Patent Assignment
Reel/Frame 026138/0613
Assignment of Assignor's Interest
Recorded: 2011-04-15
Pages: 10
Assignor
QIMONDA NORTH AMERICA CORP
Executed: 2011-02-21
Assignee
QIMONDA AG
GUSTAV-HEINEMANN-RING 212, MUNICH, 81379, GERMANY
Covered Properties
(122)
Bitline Leakage Limiting with Improved Voltage Regulation
Memory Using Tunneling Field Effect Transistors
Random Access Memory Including Multiple State Machines
Memory Cell Programmed Using a Temperature Controlled Set Pulse
Method for Accessing a Non-Volatile Memory via a Volatile Memory Interface
Method and Circuit for Transmitting a Memory Clock Signal
Integrated Circuit Having a Phase Change Memory Cell Including a Narrow Active Region Width
Method and System for Trimming Voltage or Current References
Random Access Memory That Selectively Provides Data to Amplifiers
Integrated Circuit with Memory Having a Step-Like Programming Characteristic
Integrated Circuit Having Memory Having a Step-Like Programming Characteristic
Phase Change Memory Cell Including Nanocomposite Insulator
Integrated Circuit to Identify Read Disturb Condition in Memory Cell
Lithography systems and methods
Application:
11/509,367 →
Publication:
US 2008/0050680
Resistive Memory Having Shunted Memory Cells
Semiconductor Device Including Multi-Bit Memory Cells and a Temperature Budget Sensor
Method and Apparatus for Communicating Command and Address Signals
Error Correction in Memory Devices
Method and Apparatus for Increasing Clock Frequency and Data Rate for Semiconductor Devices
Memory Including Deep Power Down Mode
System That Prevents Reduction in Data Retention
Resistive Memory Including Selective Refresh Operation
Resistive Memory Including Refresh Operation
Memory Cell with Trigger Element
Semiconductor Devices and Methods of Manufacture Thereof
Circuit and Method for Suppressing Gate Induced Drain Leakage
Die and Wafer Failure Classification System and Method
Delayed Sense Amplifier Multiplexer Isolation
Programmable Sense Amplifier Multiplexer Circuit with Dynamic Latching Mode
Multi-Component Module Fly-by Output Alignment Arrangement and Method
Multi-Bit Resistive Memory
Method and Apparatus for Selectively Utilizing Information Within a Semiconductor Device
Pillar Phase Change Memory Cell
Semiconductor Devices and Methods of Manufacture Thereof
Memory Refresh System and Method
High Density Memory Array for Low Power Application
Power Savings for Memory with Error Correction Mode
Abbreviated Burst Data Transfers for Semiconductor Memory
Multi-Mode Voltage Supply Circuit
Reduced-Delay Clocked Logic
Configurable Memory Data Path
Memory Configured on a Common Substrate
Resistive Memory Including Buried Word Lines
Method to Prevent Overreset
Stacked Sonos Memory
Multi-Level Resistive Memory Cell Using Different Crystallization Speeds
Memory Including Write Circuit for Providing Multiple Reset Pulses
Circuit and Method to Find Wordline-Bitline Shorts in a Dram
Peak Power Reduction Using Fixed Bit Inversion
Integrated Circuit Having Contact Including Material Between Sidewalls
Memory Having Shared Storage Material
Integrated Circuit Including Logic Portion and Memory Portion
Memory Refresh System and Method
Circuit for Programming a Memory Element
Integrated Circuit Including Vertical Diode
Integrated Circuit Including Vertical Diode
Memory Device Having Drift Compensated Read Operation and Associated Method
Integrated Circuit Including Contact Contacting Bottom and Sidewall of Electrode
Application:
11/766,819 →
Publication:
US 2008/0316793
Integrated Circuit Having Multilayer Electrode
Mushroom Phase Change Memory Having a Multilayer Electrode
Program Method with Locally Optimized Write Parameters
Integrated Circuit Including Resistivity Changing Material Having a Planarized Surface
Multiple Write Configurations for a Memory Cell
Voltage Regulator Pole Shifting Method and Apparatus
Conditioning Operations for Memory Cells
Voltage Regulator Startup Method and Apparatus
Method and Apparatus for Enabling a Voltage Regulator
Integrated Circuit Including Force-Filled Resistivity Changing Material
Integrated Circuit Including Multiple Memory Devices
System and Method for Monitoring Temperature in a Multiple Die Package
System and Method for Addressing Errors in a Multiple-Chip Memory Device
Method of Using Hot-Carrier-Injection Degradation as a Programmable Fuse/Switch
Method of Flexible Memory Segment Assignment Using a Single Chip Select
Method of Simple Chip Select for Memory Subsystems
Method for Self-Test and Self-Repair in a Multi-Chip Package Environment
Method and Apparatus for Adjusting the Timing of an Electronic Circuit
Structure to Share Internally Generated Voltages Between Chips in Mcp
Method and Apparatus for Synchronizing Memory Enabled Systems with Master-Slave Architecture
Method and Apparatus for Implementing Memory Enabled Systems Using Master-Slave Architecture
Sense Amplifier Biasing Method and Apparatus
Self-Diagnostic Scheme for Detecting Errors
Self-Adapted Bus Inversion
Patent:
7,522,073 →
Application:
11/947,914 →
Memory Refresh Method and Apparatus
Method and Apparatus for Using a Variable Page Length in a Memory
Integrated Circuit Including Quench Devices
Integrated Circuit Including Diode Memory Cells
Integrated Circuit Including Calibration Circuit
Enable Signal Generator Counteracting Delay Variations for Producing a Constant Sense Amplifier Enable Signal and Methods Thereof
Method and Device for Redundancy Replacement in Semiconductor Devices Using a Multiplexer
Integrated Circuit Including an Ecc Error Counter
Semiconductor Memory Having a Bank with Sub-Banks
System and Method for Signal Adjustment
Multi-Chip Package with Interconnected Stacked Chips
Integrated Circuit Fabricated Using an Oxidized Polysilicon Mask
Integrated Circuit Including an Electrode Having an Outer Portion with Greater Resistivity
Memory That Retains Data When Switching Partial Array Self Refresh Settings
Termination Switching Based on Data Rate
Derivative Logical Output
Multi-Bank Memory Device Method and Apparatus
Integrated Circuit Including Memory Refreshed Based on Temperature
Memory Including Periphery Circuitry to Support a Portion or All of the Multiple Banks of Memory Cells
System and method for controlling a semiconductor manufacturing process
Application:
12/071,721 →
Publication:
US 2009/0215206
Electronic System That Adjusts Dll Lock State Acquisition Time
Integrated Circuit That Stores First and Second Defective Memory Cell Addresses
Integrated Circuit That Stores Defective Memory Cell Addresses
Method and Apparatus for Selectively Disabling Termination Circuitry
Integrated Circuit Including Selectable Address and Data Multiplexing Mode
Multi-Mode Bus Inversion Method and Apparatus
Memory Data Bus Placement and Control
Application:
12/209,542 →
Publication:
US 2010/0070676
System and Method for Packaged Memory
Apparatus for the Dynamic Detection, Selection and Deselection of Leaking Decoupling Capacitors
Application:
12/239,575 →
Publication:
US 2010/0079150
Apparatus for the Dynamic Detection, Selection and Deselection of Leaking Decoupling Capacitors
Memory Device Refresh Method and Apparatus
Integrated Circuit with Control Circuit for Performing Retention Test
Method and Apparatus for Performing Internal Hidden Refreshes While Latching Read/Write Commands, Address and Data Information for Later Operation
Method and Apparatus to Reduce Power Consumption by Transferring Functionality from Memory Components to a Memory Interface
Digitally Controlled Cml Buffer
Memory Device Including an Electrode Having an Outer Portion with Greater Resistivity
Memory Including Vertical Bipolar Select Device and Resistive Memory Element
Method for Fabricating an Integrated Circuit Including Resistivity Changing Material Having a Planarized Surface
Apparatus and Method for Manufacturing a Multiple-Chip Memory Device with Multi-Stage Testing
System and Method for Signal Adjustment
Related Assignments
(23)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jun 9, 2006
From: NIRSCHL, THOMAS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 017752/0171 →
Assignment of Assignor's Interest
Jul 5, 2006
From: FREEBERN, MARGARET CLARK
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 017874/0243 →
Assignment of Assignor's Interest
Jul 24, 2006
From: PHILIPP, JAN BORIS; HAPP, THOMAS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 017983/0864 →
Assignment of Assignor's Interest
Jul 31, 2006
From: HAPP, THOMAS; PHILIPP, JAN BORIS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018022/0699 →
Assignment of Assignor's Interest
Jul 31, 2006
From: PHILIPP, JAN BORIS; HAPP, THOMAS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018022/0535 →
Assignment of Assignor's Interest
Jul 31, 2006
From: CHUNG, JIYOON; KIEHL, OLIVER
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018022/0755 →
Assignment of Assignor's Interest
Aug 14, 2006
From: HAPP, THOMAS; PHILIPP, JAN BORIS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018097/0293 →
Assignment of Assignor's Interest
Aug 14, 2006
From: LEWISON, RICHARD; ACIERNO, VINCENT; HUMMLER, KLAUS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018100/0505 →
Assignment of Assignor's Interest
Aug 14, 2006
From: HAPP, THOMAS; PHILIPP, JAN BORIS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018098/0201 →
Assignment of Assignor's Interest
Aug 14, 2006
From: PHILIPP, JAN BORIS; HAPP, THOMAS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018097/0291 →
Assignment of Assignor's Interest
Aug 14, 2006
From: KAO, ROM-SHEN
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018098/0153 →
Assignment of Assignor's Interest
Oct 18, 2006
From: BRANDL, STEFAN
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018405/0682 →
Assignment of Assignor's Interest
Nov 1, 2006
From: OH, JONG-HOON
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018462/0906 →
Assignment of Assignor's Interest
Nov 1, 2006
From: OH, JONG-HOON
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018462/0928 →
Assignment of Assignor's Interest
Nov 1, 2006
From: HAPP, THOMAS; PHILIPP, JAN BORIS; NIRSCHL, THOMAS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018462/0867 →
Assignment of Assignor's Interest
Dec 1, 2006
From: PHILIPP, JAN BORIS; HAPP, THOMAS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 018572/0073 →
Assignment of Assignor's Interest
Sep 24, 2007
From: NIRSCHL, THOMAS
To: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
Reel/Frame 019867/0905 →
Assignment of Assignor's Interest
Sep 26, 2007
From: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
To: INFINEON TECHNOLOGIES AG
Reel/Frame 019879/0676 →
Assignment of Assignor's Interest
Sep 27, 2007
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 019887/0645 →
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest
Nov 19, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037147/0487 →
Assignment of Assignor's Interest
Nov 30, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037171/0719 →
Assignment of Assignor's Interest
Dec 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037254/0782 →