Integrated circuit including multiple memory devices

1. An integrated circuit comprising:

a data bus having a plurality of signal conductor lines;

a first memory device directly coupled to the data bus, the first memory device to provide a first not ready signal on a predetermined one of the plurality of signal conductor lines in response to an initialization of a power-up sequence of the first memory device and to provide a first ready signal on the predetermined one of the plurality of signal conductor lines in response to completing the power-up sequence of the first memory device;

a second memory device directly coupled to the data bus, the second memory device to provide a second not ready signal on a predetermined another of the plurality of signal conductor lines in response to an initialization of a power-up sequence of the second memory device and to provide a second ready signal on the predetermined another of the plurality of signal conductor lines in response to completing the power-up sequence of the second memory device; and

a controller directly coupled to the data bus, the controller to receive the first not ready signal and the first ready signal from the first memory device via the predetermined one of the plurality of signal conductor lines, to receive the second not ready signal and the second ready signal from the second memory device via the predetermined another of the plurality of signal conductor lines, and to access the first memory device and the second memory device based on the first ready signal and the second ready signal;

wherein the first memory device is configured to input or output data on the predetermined one of the plurality of signal conductor lines after the controller accesses the first memory; and

wherein the second memory device is configured to input or output data on the predetermined another of the plurality of signal conductor lines after the controller accesses the second memory.

2. The integrated circuit of claim 1 , wherein the first memory device comprises a non-volatile memory device, and

wherein the second memory device comprises a volatile memory device.

3. The integrated circuit of claim 2 , further comprising:

a data mask line directly coupled to the second memory device and directly coupled to the controller,

wherein the first memory device is to provide the first not ready signal and the first ready signal on a data line of the data bus, and

wherein the second memory device is to provide the second not ready signal and the second ready signal on the data mask line.

4. The integrated circuit of claim 3 , wherein the controller is to access the first memory device in response to the first ready signal and access the second memory device in response to the second ready signal.

5. The integrated circuit of claim 1 , wherein the first memory device is to provide the first not ready signal and the first ready signal on a first data line of the data bus, and

wherein the second memory device is to provide the second not ready signal and the second ready signal on a second data line of the data bus.

6. The integrated circuit of claim 5 , wherein the controller is to access the first memory device and the second memory device in response to receiving both the first ready signal and the second ready signal.

7. A system comprising:

a host; and

a memory communicatively coupled to the host, the memory comprising:

a data bus having a plurality of signal conductor lines;

a first memory device to provide a first not ready signal on a predetermined one of the plurality of signal conductor lines in response to an initialization of a power-up sequence of the first memory device and to provide a first ready signal on the predetermined one of the plurality of signal conductor lines in response to completing the power-up sequence of the first memory device;

a second memory device to provide a second not ready signal on a predetermined another of the plurality of signal conductor lines in response to an initialization of a power-up sequence of the second memory device and to provide a second ready signal on the predetermined another of the plurality of signal conductor lines in response to completing the power-up sequence of the second memory device; and

a controller for receiving the first not ready signal and the first ready signal from the first memory device via the predetermined one of the plurality of signal conductor lines, for receiving the second not ready signal and the second ready signal from the second memory device via the predetermined another of the plurality of signal conductor lines, and for accessing the first memory device and the second memory device based on the first ready signal and the second ready signal; and

wherein the first memory device is configured to input or output data on the predetermined one of the plurality of signal conductor lines after the controller accesses the first memory; and

wherein the second memory device is configured to input or output data on the predetermined another of the plurality of signal conductor lines after the controller accesses the second memory.

8. The system of claim 7 , wherein the first memory device comprises a non-volatile memory device, and

wherein the second memory device comprises a volatile memory device.

9. The system of claim 7 , wherein the first memory device is to output the first not ready signal and the first ready signal on a data mask line, the data mask line directly coupled between the first memory device, the second memory device, and the controller; and

wherein the second memory device is to output the second not ready signal and the second ready signal on the data mask line.

10. The system of claim 7 , wherein the first memory device is to output the first not ready signal and the first ready signal on a first data line of a data bus, the data bus directly coupled between the first memory device, the second memory device, and the controller; and

wherein the second memory device is to output the second not ready signal and the second ready signal on a second data line of the data bus.

11. The system of claim 7 , wherein the first memory device is to output the first not ready signal and the first ready signal on a data mask line, the data mask line directly coupled between the first memory device, the second memory device, and the controller; and

wherein the second memory device is to output the second not ready signal and the second ready signal on a data line of a data bus, the data bus directly coupled between the first memory device, the second memory device, and the controller.

12. The system of claim 7 , wherein the controller is to access the first memory device in response to the first ready signal before receiving the second ready signal.

13. A method for operating a memory, the method comprising:

initializing a first power-up sequence for a first memory device coupled to a data bus, the data bus having a plurality of signal conductor lines;

providing a first not ready signal from the first memory device on a predetermined one of the plurality of signal conductor lines in response to initializing the first power-up sequence;

providing a first ready signal from the first memory device on the predetermined one of the plurality of signal conductor lines in response to completing the first power-up sequence;

initializing a second power-up sequence for a second memory device coupled to the data bus;

providing a second not ready signal from the second memory device on a predetermined another of the plurality of signal conductor lines in response to initializing the second power-up sequence;

providing a second ready signal from the second memory device on the predetermined another of the plurality of signal conductor lines in response to completing the second power-up sequence;

accessing the first memory device and the second memory device based on the first ready signal provided from the first memory device and the second ready signal provided from the second memory device;

inputting data into or reading data from the first memory device using at least the redetermined one of the plurality of signal conductor lines; and

inputting data into or reading data from the second memory device using at least the predetermined another of the plurality of signal conductor lines.

14. The method of claim 13 , wherein initializing the first power-up sequence for the first memory device comprises initializing the first power-up sequence for a dynamic random access memory device, and

wherein initializing the second power-up sequence for the second memory device comprises initializing the second power-up sequence for a non-volatile memory device.

15. The method of claim 13 , wherein providing the first ready signal comprises providing the first ready signal on a first data line of the data bus,

wherein providing the second ready signal comprises providing the second ready signal on a second data line of the data bus, and

wherein accessing the first memory device and the second memory device comprises accessing the first memory device and the second memory device in response to receiving both the first ready signal and the second ready signal.

16. The method of claim 13 , wherein providing the first ready signal comprises providing the first ready signal on a data mask line,

wherein providing the second ready signal comprises providing the second ready signal on a data line of the data bus, and

wherein accessing the first memory device and the second memory device comprises accessing the first memory device in response to receiving the first ready signal and accessing the second memory device in response to receiving the second ready signal.

17. A method for operating a memory, the method comprising:

initializing a first power-up sequence for a non-volatile memory device directly coupled to a data bus;

providing a first ready signal from the non-volatile memory device through a predetermined one of a plurality of data lines of the data bus in response to completing the first power-up sequence;

initializing a second power-up sequence for a volatile memory device directly coupled to the data bus;

accessing the non-volatile memory device through the data bus in response to the completion of the first power-up sequence before the completion of the second power-up sequence;

wherein accessing the non-volatile memory device comprises accessing the non-volatile memory device in response to the first ready signal, and wherein the predetermined one of the plurality of data lines of the data bus carries data when accessing the non-volatile memory device.

18. A method for operating a memory, the method comprising:

initializing a first power-up sequence for a non-volatile memory device directly coupled to a data bus;

providing a first ready signal from the non-volatile memory device through a predetermined one of a plurality of data lines of the data bus in response to completing the first power-up sequence;

initializing a second power-up sequence for a volatile memory device directly coupled to the data bus,

providing a second ready signal from the volatile memory device through a data mask line in response to completing the second power-up sequence;

accessing the non-volatile memory device through the data bus in response to the completion of the first power-up sequence before the completion of the second power-up sequence;

accessing the volatile memory device through the data bus in response to the second ready signal; and

wherein the data mask line carries data mask signal information when accessing the volatile memory device.

19. The method of claim 17 , wherein initializing the second power-up sequence for the volatile memory device comprises initializing the second power-up sequence for a dynamic random access memory device.