Patent Assignment
Reel/Frame 037254/0782
Assignment of Assignor's Interest
Recorded: 2015-12-09
Pages: 13
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, IRELAND
Covered Properties
(210)
Memory Cell Arrangements
Data Bus Width Converter
Memory Controller, Memory Circuit and Memory System with a Memory Controller and a Memory Circuit
Phase Shift Adjusting Method and Circuit
Electronic Device, Method for Operating an Electronic Device, Memory Circuit and Method of Operating a Memory Circuit
Synchronization and Scheduling of a Dual Master Serial Channel
Resistive Memory Having Shunted Memory Cells
Method and Apparatus for Communicating Command and Address Signals
Evaluation Unit in an Integrated Circuit
Method and Apparatus for Increasing Clock Frequency and Data Rate for Semiconductor Devices
Method of Preparing a Coating Solution and a Corresponding Use of the Coating Solution for Coating a Substrate
Hard Mask Arrangement, Contact Arrangement and Methods of Patterning a Substrate and Manufacturing a Contact Arrangement
Control Component for Controlling a Semiconductor Memory Component in a Semiconductor Memory Module
Memory Including Deep Power Down Mode
Information Transmission and Reception
Resistive Memory Including Selective Refresh Operation
Resistive Memory Including Bipolar Transistor Access Devices
Resistive Memory Including Refresh Operation
Apparatus and Method for Switching an Apparatus to a Power Saving Mode
Memory Cell with Trigger Element
Semiconductor Devices and Methods of Manufacture Thereof
Circuit and Method for Suppressing Gate Induced Drain Leakage
Delayed Sense Amplifier Multiplexer Isolation
Programmable Sense Amplifier Multiplexer Circuit with Dynamic Latching Mode
Sender, Receiver and Method of Transferring Information from a Sender to a Receiver
Multi-Component Module Fly-by Output Alignment Arrangement and Method
Multi-Bit Resistive Memory
Circuit and Method for Adjusting a Voltage Drop
Method and Apparatus for Selectively Utilizing Information Within a Semiconductor Device
Concept for Interfacing a First Circuit Requiring a First Supply Voltage and a Second Supply Circuit Requiring a Second Supply Voltage
Semiconductor Devices and Methods of Manufacture Thereof
Apparatus and Method for Providing a Signal for Transmission via a Signal Line
Method of Forming an Integrated Circuit with Two Types of Transistors
Memory Refresh System and Method
Method of Producing an Integrated Circuit Having a Capacitor with a Supporting Layer
Gate Electrode Structure, Mos Field Effect Transistors and Methods of Manufacturing the Same
Interconnection Structure and Method of Manufacturing the Same
Methods of Manufacturing Semiconductor Structures
Power Savings for Memory with Error Correction Mode
Integrated Circuit and Methods of Manufacturing a Contact Arrangement and an Interconnection Arrangement
Abbreviated Burst Data Transfers for Semiconductor Memory
Multi-Mode Voltage Supply Circuit
Reduced-Delay Clocked Logic
Semiconductor Device
Integrated Circuit Having a Resistively Switching Memory and Method
Integrated Circuit Having a Resistive Switching Device
Configurable Memory Data Path
Semiconductor Memory Device with Temperature Control
Memory Module with Ranks of Memory Chips
Bus Structure, Memory Chip and Integrated Circuit
Memory Configured on a Common Substrate
Resistive Memory Including Buried Word Lines
Manufacturing Method for an Integrated Semiconductor Memory Device and Corresponding Semiconductor Memory Device
Method to Prevent Overreset
Carbon Memory
Circuit
Zirconium Oxide Based Capacitor and Process to Manufacture the Same
Semiconductor Device, an Electronic Device and a Method for Operating the Same
Integrated Circuit Having a Memory Cell Array and Method of Forming an Integrated Circuit
Circuit Having a Clock Signal Synchronizing Device with Capability to Filter Clock-Jitter
Stacked Sonos Memory
Semiconductor Device, Method for Manufacturing Semiconductor Devices and Mask Systems Used in the Manufacturing of Semiconductor Devices
Multi-Level Resistive Memory Cell Using Different Crystallization Speeds
Memory Including Write Circuit for Providing Multiple Reset Pulses
Circuit and Method to Find Wordline-Bitline Shorts in a Dram
Integrated Circuit Device Having Openings in a Layered Structure
Peak Power Reduction Using Fixed Bit Inversion
Methods for Generating Sublithographic Structures.
Apparatus and Method for Determining Trench Parameters
Integrated Circuit Memory Device Responsive to Word Line/Bit Line Short-Circuit
Semiconductor Memory Arrangement
Integrated Circuit Having Contact Including Material Between Sidewalls
Integrated Circuit Including Logic Portion and Memory Portion
Integrated Circuit Including Spacer Defined Electrode
Memory Refresh System and Method
Wafer Inspection System and Method
Integrated Circuit Including Vertical Diode
Integrated Circuit Including Vertical Diode
Memory Device Having Drift Compensated Read Operation and Associated Method
Mushroom Phase Change Memory Having a Multilayer Electrode
Program Method with Locally Optimized Write Parameters
Integrated Circuit Including Resistivity Changing Material Having a Planarized Surface
Integrated Circuit, Intermediate Structure and a Method of Fabricating a Semiconductor Structure
Multiple Write Configurations for a Memory Cell
Memory for Providing a Graphic Content
Lithography Mask, Rewritable Mask, Process for Manufacturing a Mask, Device for Processing a Substrate, Lithographic System and a Semiconductor Device
Voltage Regulator Pole Shifting Method and Apparatus
Conditioning Operations for Memory Cells
Voltage Regulator Startup Method and Apparatus
Method and Apparatus for Enabling a Voltage Regulator
Integrated Circuit Including Force-Filled Resistivity Changing Material
Integrated Circuit Including Multiple Memory Devices
Temperature Sensor, Integrated Circuit, Memory Module, and Method of Collecting Temperature Treatment Data
Method for Classifying Memory Cells in an Integrated Circuit
Method for Manufacturing an Integrated Circuit Including a Transistor
System and Method for Monitoring Temperature in a Multiple Die Package
System and Method for Addressing Errors in a Multiple-Chip Memory Device
Memory circuit with field effect transistor and method for manufacturing a memory circuit with field effect transistor
Method of Using Hot-Carrier-Injection Degradation as a Programmable Fuse/Switch
Arrangement of Stacked Integrated Circuit Dice Having a Direct Electrical Connection
Method for Forming a Structure on a Substrate and Device
Integrated Circuit Device for Receiving Differential and Single-Ended Signals
Semiconductor Memory Arrangement
Integrated Circuit, Chip Stack and Data Processing System
Method and Device for Enumeration
Clock Signal Synchronizing Device with Inherent Duty-Cycle Correction Capability
Integrated Circuit and Method of Operating the Same
Integrated Circuits, Micromechanical Devices, and Method of Making Same
Method of Fabricating an Integrated Circuit
Method of Flexible Memory Segment Assignment Using a Single Chip Select
Method for Self-Test and Self-Repair in a Multi-Chip Package Environment
Integrated Circuit Including Structures Arranged at Different Densities and Method of Forming the Same
Sensor, Method for Sensing, Measuring Device, Method for Measuring, Filter Component, Method for Adapting a Transfer Behavior of a Filter Component, Actuator System and Method for Controlling an Actuator Using a Sensor
Integrated Circuit and Method of Manufacturing an Integrated Circuit
Mask with Registration Marks and Method of Fabricating Integrated Circuits
Integrated Circuit, Circuit System, and Method of Manufacturing
Method of Fabricating a Semiconductor Device
Apparatus and Method of Operating an Integrated Circuit
Data Conversion
Electric Device, Stack of Electric Devices, and Method of Manufacturing a Stack of Electric Devices
Integrated Circuit and Method of Generating a Bias Signal for a Data Signal Receiver
Memory Module System and Method for Operating a Memory Module
Structure to Share Internally Generated Voltages Between Chips in Mcp
Method and Structure of Expanding, Upgrading, or Fixing Multi-Chip Package
Integrated Circuit and Methods of Manufacturing the Same
Method and Apparatus for Memory Access Optimization
Memory System and Method for Using a Memory System with Virtual Address Translation Capabilities
Scanning Probe Microscopy Cantilever, Corresponding Manufacturing Method, Scanning Probe Microscope, and Scanning Method
Buffer Circuit for a Memory Module
An Integrated Circuit Including Different Types of Gate Stacks and Corresponding Intermediate Integrated Circuit Structure
Method and Apparatus for Synchronizing Memory Enabled Systems with Master-Slave Architecture
Memory Module System
Method and Apparatus for Implementing Memory Enabled Systems Using Master-Slave Architecture
Integrated Circuit Including Doped Semiconductor Line Having Conductive Cladding
Method and Apparatus for an Integrated Circuit with Programmable Memory Cells, Data System
System and Method for Establishing Data Connections Between Electronic Devices
Integrated Circuit Having Memory Cells and Method of Manufacture
A System for Electronic Components Mounted on a Circuit Board
Self-Diagnostic Scheme for Detecting Errors
Conductive Line Comprising a Capping Layer
Self-Adapted Bus Inversion
Patent:
7,522,073 →
Application:
11/947,914 →
Method of Refreshing Data in a Storage Location Based on Heat Dissipation Level and System Thereof
Memory Refresh Method and Apparatus
Method and Apparatus for Using a Variable Page Length in a Memory
Integrated Circuit Including Quench Devices
Integrated Circuit Including Diode Memory Cells
Semiconductor Device with a Plurality of One Time Programmable Elements
Integrated Circuit Including Calibration Circuit
Semiconductor Device with Chip Mounted on a Substrate
Enable Signal Generator Counteracting Delay Variations for Producing a Constant Sense Amplifier Enable Signal and Methods Thereof
Method for Structuring a Substrate Using a Metal Mask Layer Formed Using a Galvanization Process
Method and Device for Redundancy Replacement in Semiconductor Devices Using a Multiplexer
Memory System with Cyclic Redundancy Check
Integrated Circuit Including an Ecc Error Counter
Integrated Semiconductor Memory and Method for Operating a Data Path in a Semiconductor Memory
Method and System for Testing an Integrated Circuit
Method for Manufacturing a Wafer Level Package
System and Method for Signal Adjustment
Integrated Circuit with Buried Control Line Structures
Multi-Chip Package with Interconnected Stacked Chips
Carbon Diode Array for Resistivity Changing Memories
Integrated Circuit with Resistive Memory Cells and Method for Manufacturing Same
Semiconductor Device Chip, Semiconductor Device System, and Method
Semiconductor Memory Device and Method with a Changeable Substrate Potential
Integrated Circuit and Method Including an Isolation Arrangement
Reduced-Stress Through-Chip Feature and Method of Making the Same
Methods and Apparatuses for Generating a Random Sequence of Commands for a Semiconductor Device
Interface Device, Circuit Module, Circuit System, Device for Data Communications and Method for Calculating a Circuit Module
Prober Apparatus and Operating Method Therefor
Circuits and Methods for Error Coding Data Blocks
Concept for Reducing Crosstalk
Device and Method for Electrical Contacting Semiconductor Devices for Testing
Test Method, Integrated Circuit and Test System
Integrated Circuit and Method for Producing the Same
Methods of Compensating Lens Heating, Lithographic Projection System and Photo Mask
Integrated Circuit Including a Capacitor and Method
Method and Device for Transmitting Outgoing Useful Signals and an Outgoing Clock Signal
Integrated Circuit with Floating-Gate Electrodes Including a Transition Metal and Corresponding Manufacturing Method
Memory Module Having Buffer and Memory Ranks Addressable by Respective Selection Signal
Chip, Multi-Chip System in a Method for Performing a Refresh of a Memory Array
Electronic System That Adjusts Dll Lock State Acquisition Time
System Including Preemphasis Driver Circuit and Method
Method and Integrated Circuit for Determining the State of a Resistivity Changing Memory Cell
Integrated Circuit and Method Including Structuring a Material
Device with Precharge/Homogenize Circuit
Integrated Circuit Comprising an Amorphous Region and Method of Manufacturing an Integrated Circuit
Method of Forming an Integrated Circuit with NAND Flash Array Segments and Intra Array Multiplexers and Corresponding Integrated Circuit with NAND Flash Array Segments and Intra Array Multiplexers
Integrated Logic Circuit and Method for Producing an Integrated Logic Circuit
Integrated Circuit and Method for Charge Reversal of a Circuit Part of the Integrated Circuit
Memory Module
Method of Operating a Memory Apparatus, Memory Device and Memory Apparatus
Integrated Circuit and Method of Forming an Integrated Circuit
Semiconductor Memory and Method for Operating a Semiconductor Memory
Method of Operating a Memory Apparatus, Memory Device and Memory Apparatus
Array of Low Resistive Vertical Diodes and Method of Production
Memory Device Having an Evaluation Circuit
Heat Transfer System for Memory Modules
Integrated Circuit
Apparatus for the Dynamic Detection, Selection and Deselection of Leaking Decoupling Capacitors
Control Circuit in a Memory Chip
Method for Producing an Integrated Circuit and Arrangement Comprising a Substrate
Integrated Circuit Comprising a Thyristor and Method of Controlling a Memory Cell Comprising a Thyristor
Integrated Circuit Comprising Conductive Lines and Contact Structures and Method of Manufacturing an Integrated Circuit
Memory Including Vertical Bipolar Select Device and Resistive Memory Element
Method for Fabricating an Integrated Circuit Including Resistivity Changing Material Having a Planarized Surface
Apparatus and Method for Manufacturing a Multiple-Chip Memory Device with Multi-Stage Testing
System and Method for Signal Adjustment
Phase Shift Adjusting Method and Circuit
Integrated Circuit Having a Material Structured by a Projection
Circuit