IP Library Granted Patent US 7,719,886
Granted Patent B2
US 7,719,886 · App. 11/743,987 · Granted May 18, 2010

Multi-level resistive memory cell using different crystallization speeds

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,719,886
App. No.
11/743,987
Granted
May 18, 2010
Kind
B2
Abstract

An integrated circuit includes a first electrode and a second electrode. The integrated circuit includes a first resistivity changing material between the first electrode and the second electrode and a second resistivity changing material between the first electrode and the second electrode. The first resistivity changing material and the second resistivity changing material have different crystallization speeds.

Claims (42)

1. An integrated circuit comprising:

a first electrode;

a second electrode;

a first resistivity changing material between the first electrode and the second electrode; and

a second resistivity changing material between the first electrode and the second electrode;

wherein the first resistivity changing material and the second resistivity changing material have different crystallization speeds, and

wherein the first electrode, the second electrode, the first resistivity changing material, and the second resistivity changing material are aligned.

2. The integrated circuit of claim 1 , further comprising:

a diffusion barrier between the first resistivity changing material and the second resistivity changing material.

3. The integrated circuit of claim 1 , further comprising:

shunt resistors surrounding at least one of the first resistivity changing material and the second resistivity changing material.

4. The integrated circuit of claim 1 , wherein the first resistivity changing material and the second resistivity changing material have different cross-sectional widths.

5. A memory cell comprising:

a first electrode;

a first resistivity changing material directly contacting the first electrode and vertically adjacent the first electrode;

a second resistivity changing material vertically adjacent the first resistivity changing material; and

a second electrode directly contacting the second resistivity changing material,

wherein the first resistivity changing material and the second resistivity changing material have different crystallization speeds.

6. The memory cell of claim 5 , further comprising:

a diffusion barrier directly contacting the first resistivity changing material and the second resistivity changing material.

7. The memory of cell of claim 6 , wherein the diffusion barrier comprise one of TiN, TaN, W, Al, WN, TaSiN, TiSiN, TiAlN, C, and Cu.

8. The memory of cell of claim 5 , wherein the first electrode and the second electrode comprise one of TiN, TaN, W, Al, WN, TaSiN, TiSiN, TiAlN, C and Cu.

9. The memory cell of claim 5 , further comprising:

shunt resistors laterally surrounding at least one of the first resistivity changing material and the second resistivity changing material.

10. The memory cell of claim 5 , wherein the first resistivity changing material and the second resistivity changing material have different cross-sectional widths.

11. The memory cell of claim 5 , further comprising:

insulation material laterally surrounding the first electrode, the first resistivity changing material, the second resistivity changing material, and the second electrode.

12. A memory cell comprising:

a first electrode;

a first phase change material layer over the first electrode;

a second phase change material layer over the first phase change material layer; and

a second electrode over the second phase change material layer,

wherein the first phase change material layer and the second phase change material layer have different crystallization speeds.

13. The memory cell of claim 12 , further comprising:

a diffusion barrier between the first phase change material layer and the second phase change material layer.

14. The memory of cell of claim 13 , wherein the diffusion barrier comprise one of TiN, TaN, W, Al, WN, TaSiN, TiSiN, TiAlN, C, and Cu.

15. The memory of cell of claim 12 , wherein the first electrode and the second electrode comprise one of TiN, TaN, W, Al, WN, TaSiN, TiSiN, TiAlN, C and Cu.

16. The memory cell of claim 12 , further comprising:

shunt resistors laterally surrounding at least one of the first phase change material layer and the second phase change material layer.

17. The memory cell of claim 12 , wherein the first phase change material layer and the second phase change material layer have different cross-sectional widths.

18. The memory cell of claim 12 , further comprising:

insulation material laterally surrounding the first electrode, the first phase change material layer, the second phase change material layer, and the second electrode.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037254/0782 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2011
From: QIMONDA NORTH AMERICA CORP
To: QIMONDA AG
Reel/Frame 026138/0613 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2007
From: PHILIPP, JAN BORIS; HAPP, THOMAS
To: QIMONDA NORTH AMERICA CORP.
Reel/Frame 019454/0996 →