Integrated circuit and method including an isolation arrangement
View Patent ↗An integrated circuit and method including an isolation arrangement. One embodiment provides a substrate having trenches and mesa regions and also auxiliary structures on the mesa regions. A first isolation structure covers side walls and a bottom region of the trenches and at least partially side walls of the auxiliary structure. A liner on the first isolation structure fills the trenches and gaps between the auxiliary structures with a second isolation structure; and the second isolation structure is pulled back, wherein upper sections of the liner are uncovered.
1. A method for producing an integrated circuit including an isolation arrangement comprising:
providing a substrate having trenches and mesa regions and also auxiliary structures on the mesa regions;
providing a first isolation structure, which covers side walls and a bottom region of the trenches and at least partially covers side walls of the auxiliary structure;
providing a liner on the first isolation structure;
filling the trenches and gaps between the auxiliary structures with a second isolation structure; and pulling back the second isolation structure, wherein upper sections of the liner are uncovered;
partially removing the auxiliary structures prior to uncovering the liner sections; and
reinforcing the auxiliary structure to form useful structures.
2. The method of claim 1 , comprising removing the uncovered upper sections of the liner.
3. The method of claim 1 , wherein the second isolation structure initially extends above the mesa regions, and wherein pulling back the second isolation structure comprises pulling back the second isolation structure at most as far as a top side of the mesa regions.
4. The method of claim 1 , comprising pulling back the second isolation structure as far as below a top side of the mesa regions.
5. The method of claim 1 , comprising wherein the first isolation structure fills a lower region of the trenches.
6. The method of claim 1 , comprising pulling back the first isolation structure in a bottom region of the trenches.
7. The method of claim 1 , comprising selecting a material of the liner from a group consisting of silicon nitride, polysilicon and hafnium oxide.
8. A method for producing a nonvolatile memory device comprising:
providing a substrate having trenches and mesa regions and also auxiliary structures on the mesa regions;
providing a first isolation structure, which covers side walls and a bottom region of the trenches and at least partially covers side walls of the auxiliary structures;
providing a liner on the first isolation structure;
filling the trenches and gaps between the auxiliary structures with a second isolation structure; and pulling back the second isolation structure, wherein upper sections of the liner are uncovered; and
forming floating gates at least partially instead of the auxiliary structures; wherein lower sections of the auxiliary structures respectively form a part of the respective floating gate and an upper section of the auxiliary structures above the respective lower section is respectively removed and a second part of the respective floating gate is respectively formed prior to at least partially uncovering the liner.
9. The method of claim 8 , comprising removing the upper sections of the liner.
10. The method of claim 8 , wherein the second isolation structure initially extends above the mesa regions, and wherein pulling back the second isolation structure comprises pulling back the second isolation structure at most as far as a top side of the mesa regions.
11. The method of claim 8 , comprising pulling back the second isolation structure as far as below a top side of the mesa regions.
12. The method of claim 8 , comprising wherein the first isolation structure fills a lower region of the trenches.
13. The method of claim 8 , comprising pulling back the first isolation structure in a bottom region of the trenches.
14. The method of claim 8 , comprising selecting a material of the liner from a group consisting of silicon nitride, polysilicon and hafnium oxide.