Method of forming an integrated circuit with two types of transistors
View Patent ↗An integrated circuit includes a transistor of a first type with a first gate electrode and a transistor of a second type with a second gate electrode. The first gate electrode is formed in a first gate groove that is defined in a semiconductor substrate, and the second gate electrode is formed in a second gate groove defined in the semiconductor substrate. The first gate electrode completely fills a space between two adjacent first isolation trenches, and the second gate electrode partially fills a space between two adjacent second isolation trenches, with substrate portions being arranged between the second gate electrode and the adjacent second isolation trenches, respectively.
1. A method of manufacturing an integrated circuit, comprising:
forming a transistor of a first type comprising a first gate electrode formed in a first gate groove that is defined in a semiconductor substrate between first and second source/drain regions of the transistor of the first type, the first gate electrode completely filling a space between two adjacent first isolation trenches in a cross section along the first gate electrode perpendicular to a first direction defined by a line extending between the first and second source/drain regions; and
forming a transistor of a second type comprising a second gate electrode formed in a second gate groove defined in the semiconductor substrate, the second gate electrode partially filling a space between two adjacent second isolation trenches in a cross section along the second gate electrode perpendicular to the first direction, wherein portions of the semiconductor substrate are arranged between the second gate electrode and the adjacent second isolation trenches on both sides of the second gate electrode in the cross section along the second gate electrode perpendicular to the first direction.
2. The method of claim 1 , wherein the first gate groove and the second gate groove are defined by common etching processes.
3. The method of claim 2 , wherein the first gate groove and the second gate groove are defined by an etching process which removes a substrate material between adjacent isolation grooves and leaves substrate portions between the first gate groove and the adjacent first isolation trenches and between the second gate groove and the adjacent second isolation trenches.
4. The method of claim 3 , further comprising
selectively etching the substrate material between the first gate groove and the adjacent first isolation trenches, wherein the substrate portions between the second gate groove and the adjacent second isolation trenches remain.
5. The method of claim 1 , further comprising:
etching a portion in the isolation trenches adjacent to the first gate groove so as to define plate-like portions of the first gate electrode.
6. The method of claim 1 , further comprising:
forming a planar transistor above the semiconductor substrate, the planar transistor comprising a third gate electrode.
7. The method of claim 1 , wherein the transistor of the first type is a corner device.
8. The method of claim 1 , wherein an angle β between a normal to the substrate surface and a sidewall of at least one of the first and the second isolation trenches is greater than 15°.
9. The method of claim 1 , wherein a portion of the second gate electrode is formed in the adjacent second isolation trenches.
10. The method of claim 1 , wherein the substrate portions have a surface disposed more than 10 nm below a surface of the semiconductor substrate.
11. The method of claim 1 , wherein the transistor of the first type is formed in a memory array portion of the semiconductor substrate and the transistor of the second type is formed in a peripheral portion of the semiconductor substrate, separate from the memory array.
12. The method of claim 1 , wherein the transistor of the first type is formed with a different threshold voltage than a threshold voltage of the transistor of the second type.