Peak power reduction using fixed bit inversion

1. A semiconductor device comprising:

a first circuit block;

a second circuit block;

a data bus coupled between the first and second circuit blocks;

means for inverting a selected segment of data that is transferred onto the data bus and for re-inverting the selected segment of data before the data is transferred off the data bus without first analyzing the data to determine the selected segment of data that is inverted and for not inverting a remaining segment of data that is transferred by the data bus.

2. The semiconductor device of claim 1 , further comprising a first data inverter on the data bus for inverting the selected segment of data that is transferred onto the data bus.

3. The semiconductor device of claim 2 , further comprising a second data inverter at an end of the data bus for re-inverting the selected segment of data before the data is transferred off the data bus.

4. The memory component of claim 2 , wherein the first data inverter is located at the half way point on the data bus.

5. A memory component comprising:

a first circuit block;

a second circuit block;

a data bus coupled between the first and second circuit blocks;

control circuitry for designating a selected segment of data for inversion on the data bus and designating a remaining segment of data for no inversion on the data bus;

a first data inverter on the data bus for inverting the selected segment of data that is transferred onto the data bus; and

a second data inverter at an end of the data bus for re-inverting the selected segment of data before the data is transferred off the data bus;

wherein the data that is transferred onto the data bus is not analyzed in order to determine the selected segment of data that is inverted.

6. The memory component of claim 5 , wherein the first data inverter is located at the half way point on the data bus.

7. The memory component of claim 6 , wherein the half way point on the data bus is approximately one half of the total physical length of the data bus.

8. The memory component of claim 6 , wherein the half way point on the data bus is such that the portions of the data bus on either side of the first inversion circuit have approximately the same amount of coupling current consumption in transferring data.

9. A semiconductor device comprising:

a first circuit block;

a second circuit block;

a data bus coupling the first and second circuit blocks, the data bus configured to transmit data and having a first segment and a second segment;

wherein a selected portion of the data is inverted for one of the first and second segments and not inverted for the other of the first and second segments, both segments being transmitted on the data bus.

10. The semiconductor device of claim 9 , wherein each of the first and second segments are approximately one-half of the length of the data bus.

11. The semiconductor device of claim 9 , wherein each of the first and second segments have approximately the same amount of coupling current consumption in transferring data.

12. The semiconductor device of claim 9 , wherein the data bus is comprised of a plurality of parallel metal lines.

13. The semiconductor device of claim 9 , characterized in that no analysis is performed on data in order to determine which portion of the data is the selected portion for inversion.

14. The semiconductor device of claim 9 , wherein the data bus configured to transmit data bursts and the selected portion of the data comprises one half of the total amount of bursts transmitted.

15. A method for transferring data comprising:

transferring data onto a data bus;

transmitting a selected segment of the data for approximately half of the data bus in a non-inverted form;

inverting the selected segment of data;

transmitting the selected segment of the data for approximately half of the data bus in an inverting form;

re-inverting the selected segment of data before the data is transferred off the data bus;

transmitting a remaining segment of data the entire length of the data bus in non-inverted form; and

transferring the data off the data bus.

16. The method of claim 15 , wherein approximately half of the data bus is approximately one half of the total physical length of the data bus.

17. The method of claim 15 , wherein approximately half of the data bus is the length of the data bus in which approximately half of the total coupling current of the data bus is consumed in transferring data.

18. The method of claim 15 , wherein the method is characterized by the absence of analysis of the data in order to determine the selected segment of data that is inverted.

19. A method for transferring data comprising:

transferring data onto a data bus;

inverting a selected segment of the data for at least some segment of the data bus;

re-inverting the selected segment of data before the data is transferred off the data bus;

transmitting a remaining segment of data the entire length of the data bus in non-inverted form; and

transferring the data off the data bus;

wherein the method is characterized by the absence of analysis of the data in order to determine the selected segment of data that is inverted.

20. The method of claim 19 , wherein approximately half of the data bus is approximately one half of the total physical length of the data bus.

21. The method of claim 19 , wherein approximately half of the data bus is the length of the data bus in which approximately half of the total coupling current of the data bus is consumed in transferring data.